Is FPGA power design ready for concurrent engineering?

Robert Cravotta -September 24, 2014
EDN   

When designers address the power requirements and constraints for an FPGA-based design earlier in the development process, it can yield significant competitive advantage in the final implementation of the system. However, based on the repetitive invocation of this self-evident statement throughout the technical literature, is there something in today’s FPGA-based system that is making it impractical or too difficult to fully follow this advice? Despite ready access to a variety of development tools such as early power estimators and power analyzers specifically targeting FPGA-based projects, it is beneficial for power designers to consider a worst-case, rather than an optimal-case, power system early in the design process because there is still too much uncertainty in how the dynamic load requirements will fluctuate between a static, low current condition to a full processing state until the hardware design is completed and power can be measured.

Could adopting concurrent engineering (CE) practices provide a way for development teams that are using FPGA devices in their projects to more easily and quickly find and extract the most effective balance between processing performance, bill of material (BOM) cost, and energy efficiency in today’s designs? Examining how concurrent engineering impacts a team’s design efforts and how it can affect a development team’s ability to address power supplies from the beginning of the project alongside the FPGA and the rest of the system can help answer this question.

Concurrent engineering is a mechanism that enables design teams to more quickly discover and resolve disconnects in assumptions between the various disciplines that work together to produce the final design. It is highly unlikely that any development team could get all of the requirements for a complex system perfectly correct at the start of a design – as a result, it is more effective to be able to discover, identify, and abandon disconnects in assumptions and design decisions as early as possible and replace them with ones that guide the project closer to the desired outcome at the lowest possible cost.

Is the complexity and potential consequences of late design cycle and worst-case FPGA power system design sufficient to justify adopting concurrent engineering practices? To answer this we need to understand: what are the sources of design complexity and uncertainty that designers of FPGA power systems face and how do they affect the trade-offs they must make when designing the power supply?

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