Improving analog design verification using UVM
Mike Bartley, Test and Verification Solutions
EDN (March 23, 2015)
As technology becomes more integrated into our everyday life, our chips need to better communicate with the analog world. Most modern system on chip (SoC) designs therefore contain analog and mixed-signal (AMS) elements integrated with digital components. According to Sandip Ray of Intel, AMS elements currently consume about 40% of the design effort, and an estimated 50% of errors in recent chips that require a redesign are due to bugs in the AMS portion of the design [1].
This increase in AMS content in silicon creates several verification challenges: how do we verify the analog design itself, its integration with the digital, and whether the combination achieves the intended overall function? However, there is no standard or even widely adopted approach to this despite the continuous increase in analog content. One potential route is via an efficient, reusable AMS verification approach using the Universal Verification Methodology (UVM) outlined below:
To read the full article, click here
Related Semiconductor IP
- PUF FPGA-Xilinx Premium with key wrap
- ASIL-B Ready PUF Hardware Premium with key wrap and certification support
- ASIL-B Ready PUF Hardware Base
- PUF Software Premium with key wrap and certification support
- PUF Hardware Premium with key wrap and certification support
Related White Papers
- Metric Driven Verification of Reconfigurable Memory Controller IPs Using UVM Methodology for Improved Verification Effectiveness and Reusability
- Design patterns in SystemVerilog OOP for UVM verification
- Improving Verification Efficiency Using Application Specific Instruction Processors
- Improving SystemVerilog UVM Transaction Recording and Modeling
Latest White Papers
- e-GPU: An Open-Source and Configurable RISC-V Graphic Processing Unit for TinyAI Applications
- How to design secure SoCs, Part II: Key Management
- Seven Key Advantages of Implementing eFPGA with Soft IP vs. Hard IP
- Hardware vs. Software Implementation of Warp-Level Features in Vortex RISC-V GPU
- Data Movement Is the Energy Bottleneck of Today’s SoCs