Design patterns in SystemVerilog OOP for UVM verification

Dave Rich, Mentor Graphics
EDN (January 24, 2019)

SystemVerilog supports templates for generic code writing using parameterized classes. Here we’re going to describe some of the design patterns in the code that make up the UVM base class library. Users writing testbenches with the SystemVerilog Universal Verification Methodology (UVM) or any kind of class-based methodology can learn from these techniques.

Design patterns are optimized, reusable solutions to commonly occurring programming problems. They are more than just class definitions or a package of routines—they are language-independent templates for writing code.

The concept of design patterns specifically for SystemVerilog object oriented programming (OOP) languages was popularized in 1994 by the book “Design Patterns: Elements of Reusable Object-Oriented Software.” OOP enables writing reusable code. OOP design patterns take reuse another step.

There are many kinds of design patterns. This article covers two important categories:

Singleton patterns – Restrict instantiation of a class to one object.

Factory patterns – Provide an interface for creating families of related or dependent objects and specify a policy for creating them.

Before explaining these in more detail, we need to understand how SystemVerilog supports templates for writing generic code using parameterized classes.

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