Surveying the hardware-assisted verification landscape
edadesignline.com (July 30, 2008)
This year's Design Automation Conference (DAC) served as an ideal setting for checking in on the ongoing verification requirements of today's design teams and test out a few theories on hardware-assisted verification. Over the course of the four-day conference in June, the team staffing the EVE booth asked a series of questions to a sampling of DAC attendees and received some surprising and some not so surprising answers.
We met with system architects, designers, verification and validation engineers, managers and electronic design automation (EDA) tool support managers, all of whom dropped in to give us an update and check in on what we're doing. Most hold engineering staff positions and all of them graciously consented to answering a short usage survey. Additionally, most of the attendees we surveyed were designing consumer and wireless products, and the concentration was from the United States and Asia.
When asked which language they use for application specific integrated circuit (ASIC) design, 59% said Verilog, followed in order by SystemVerilog (26%), VHDL (23%) and SystemC (12%). For testbench design, Verilog continues to dominate with 38%, followed by SystemVerilog/Verification Methodology Manual (VMM) (30%), VHDL (13%), SystemC (11%) and Specman (8%), with Vera (5%) trailing behind. This indicates that there is a clear migration from traditional hardware verification languages (Specman and Vera) to SystemVerilog.
To read the full article, click here
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- CXL 3.0 Controller
- ECC7 Elliptic Curve Processor for Prime NIST Curves
Related White Papers
- Supporting hardware assisted verification with synthesizable assertions
- Is Agile coming to Hardware Development?
- Applying Continuous Integration to Hardware Design and Verification
- Implementing matrix inversions in fixed-point hardware
Latest White Papers
- TROJAN-GUARD: Hardware Trojans Detection Using GNN in RTL Designs
- How a Standardized Approach Can Accelerate Development of Safety and Security in Automotive Imaging Systems
- SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models
- Enabling Chiplet Design Through Automation and Integration Solutions
- Shift-Left Verification: Why Early Reliability Checks Matter