A brief primer on embedded SoC packaging options
Deepak Behera, Sumit Varshney, Sunaina Srivastava, and Swapnil Tiwari, Freescale Semiconductor
11/20/2011 9:16 PM EST
With shrinking technology, voltage levels are being reduced, lowering noise margins required to enable a clean design from a signal integrity perspective. Higher operating frequency requirements further complicate design closure. Semiconductor packages are a quintessential piece of the signal integrity puzzle.
This article addresses the basics of packaging such as types of packages and their advantages and disadvantages, future trends, and factors to be considered while choosing a package.
To read the full article, click here
Related Semiconductor IP
- NPU IP Core for Mobile
- NPU IP Core for Edge
- Specialized Video Processing NPU IP
- HYPERBUS™ Memory Controller
- AV1 Video Encoder IP
Related White Papers
- An Efficient Device for Forward Collision Warning Using Low Cost Stereo Camera & Embedded SoC
- Testing Of Repairable Embedded Memories in SoC: Approach and Challenges
- Internal JTAG - A cutting-edge solution for embedded instrument testing in SoC: Part 1
- Internal JTAG - A cutting-edge solution for embedded instrument testing in SoC: Part 2
Latest White Papers
- Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
- Transition Fixes in 3nm Multi-Voltage SoC Design
- CXL Topology-Aware and Expander-Driven Prefetching: Unlocking SSD Performance
- Breaking the Memory Bandwidth Boundary. GDDR7 IP Design Challenges & Solutions
- Automating NoC Design to Tackle Rising SoC Complexity