Designers confront costs of SoC scaling, integration

Designers confront costs of SoC scaling, integration
By Stephan Ohr and Anthony Cataldo, EE Times
February 5, 2002 (11:08 a.m. EST)
URL: http://www.eetimes.com/story/OEG20011109S0096

SAN FRANCISCO — Transistor voltage scaling and system-on-chip integration — two issues that have put Moore's Law to the test — will take center stage at next year's International Solid-State Circuits Conference. While next-generation processors and memories will pack as many as 250 million transistors on one chip, the roster of papers and discussions on tap for the February conference illuminates the ever-increasing cost of keeping the integration train from grinding to a halt.

A sampling of the papers makes it clear that throwing more transistors onto a chip without considering the ill effects of leakage current can no longer be taken for granted. Moreover, to reach their visions of system-on-chip grandeur, designers will have to incorporate more analog functionality — whether for wireless, audio, image processing, power savings, even clean clocks for digital functions. But so far no panacea has been found.

Yet circuit desig ners are doggedly searching for ways around such problems. Transistor voltage scaling — a blessing for performance but a curse for power consumption — has become a target as designers turn their attention to the transistor's body — the area that bridges the source and drain. Instead of treating the body as having one voltage threshold, designers are coming up with ways to tickle it with a separate current.

"Historically, body bias has remained fixed at some predefined potential, giving the illusion that the MOSFET is a three-terminal device," said Kenneth Smith, a University of Toronto professor and ISSCC promotional chairman. "The reality is that the body can be construed as a fourth terminal, since it strongly influences the threshold voltage — the potential at which the device turns on. It can be used to control device behavior."

Intel Corp., for one, will present several papers on a body bias technique developed in conjunction with MIT. Traditionally, processor makers have rel ied solely on changing the threshold voltage of a transistor to manipulate its performance or power consumption profile. Lower-V_t transistors are used in circuits where performance is critical, such as a processor's execution and arithmetic-logic units, at the expense of higher leakage current. To cut back on off-state leakage, high-V_t transistors are used where performance can be sacrificed.

Intel is proposing to take that a step further by having the body be either forward- or reverse-biased. That technique could be applied to either the high- or low-V_t transistors, effectively giving circuit designers leeway to tune both transistor types for performance or lower power.

To show how that benefits speed, Intel will describe a prototype 32-bit integer execution unit that uses dual-V_t CMOS circuits and runs at 5 GHz. The execution core is based on 0.13-micron technology. To address power, the company will describe a 1.1-V router chip that boasts a 23 percent reduction in switching power and a 3x drop in standby power, attained by withdrawing a forward bias.

An ancillary benefit is better yields. The bias technique allows devices to be adjusted to minimum turn-on thresholds after manufacturing. According to a third Intel paper, body biasing can triple the accepted die count for the highest-frequency bin.

Body bias path

Intel isn't the only one beating a path to body bias variations. Hitachi Ltd. will describe a 175-millivolt multiply-accumulate unit that uses power supply and body bias control techniques to reduce operating voltage to 14 nanowatts at 166 kHz.

While body-biasing techniques could be one way to address voltage scaling, true system-on-chip devices still elude designers. Few dispute that Moore's Law still has legs. "But SoC cost concerns require us to integrate functions that are currently realized in different technologies: logic, memory, analog power management, passives, radio and wireline," wrote Dennis Buss, the tec hnology fellow who leads the mixed-signal development group at Texas Instruments Inc. Buss will air his concerns at the beginning of the plenary sessions at ISSCC.

Indeed, analog concerns such as coping with lower supply voltages become more pressing as CMOS geometry shrinks take their toll. The performance of analog devices such as amplifiers and data converters does not scale in CMOS: Lower voltage means a loss of headroom in the form of dynamic range, slew rate and signal-to-noise ratio.

Still, designers appear to be making progress using process design rules more akin to advanced digital logic. Infineon Technologies will describe a 51-GHz VCO implemented in a standard 0.12-micron, six-metal-layer CMOS process that uses a high-inductance tank to operate with a 1-V power supply, consuming 1 mW. A second paper will tell how Infineon is leveraging the same design rules for a 25-GHz static frequency divider.

Philips Research, meanwhile, will describe a 2.4-GHz power amp based on 0.18-micron CMOS. The Infineon and Philips papers appear to be the exception; most RF-related papers still describe technologies based on 0.35- or 0.5-micron design rules.