BIST schemes for ADCs

Kushal Kamal & Vandana Sapra (Freescale)
EDN (August 29, 2014)

With an increasing number of complex circuits being integrated into SoCs, their testing requirements have become equally complex. While there are well established test strategies for digital circuits, the testing of analogue circuits is quite expensive and challenging. A commonly encountered analogue circuit is the analog to digital converter (ADC), and in this paper we will discuss the conventional method of testing ADCs, as well as the various built-in self-test schemes that can be used for their testing.

The traditional method of testing employs Automatic Test Equipment (ATE) feeding in arbitrary waveforms or test patterns to Device-Under-Test (DUT) and collecting test responses as seen in Figure 1. One popular and simplistic method to test an ADC is by a simple Ramp Test in which the ADC is configured to perform back to back conversions on a single channel. Then, a suitable ramp voltage is applied to the same channel so that all possible digital codes appear at the ADC output a fixed number of times. This output code is then compared against the expected ADC output. The difference between the expected and the actual output is calculated. The max. to min. variation of this difference is called TUE, or Total Unadjusted Error. On the test equipment, we program it to fail the part if the TUE is beyond an acceptable number. In Automotive MCUs, this figure can be up to ±2LSbs. Hence, if the ADC has a TUE of more than ±2LSbs, it is considered a bad part.

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