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Search (1,097)
Compare 1,097 IP from 52 vendors (1 - 10)
  • A memory BIST solution which has been optimized for Dolphin memories
    • + Analyze RTL design or netlist to identify memories
    • + Plan MBIST engines
    • + Insert into RTL design or netlist / Top level hookup to JTAG
    • + Verify stand-alone/ Verify partition level / Verify top level
  • USB Type-C and Power Delivery Verification IP
    • Compliant with standard USB PD Rev 3.1 V1.8, Type-C Rev2.2 & USB type C Port controller interface Rev2.0 V1.3.
    • Supports enabling USB4 (Gen 2/Gen 3/Gen 4) over type C Connectors.
    • Supports both Standard Power range (SPR) and Extended Power range (EPR) modes of operation.
    • Supports all Fixed voltage supply, Programmable power supply (PPS) and Adjustable Votlage supply (AVS).
    Block Diagram -- USB Type-C and Power Delivery Verification IP
  • Simulation VIP for MIPI D-PHY, C-PHY and A-PHY
    • PHY Monitor
    • Built-in scoreboarding between serial/PPI interface, also monitors error signal interface
    • Reports any detected error on any lane on serial interface and is not reflected on PPI interface
    • C-PHY and D-PHY
    Block Diagram -- Simulation VIP for MIPI D-PHY, C-PHY and A-PHY
  • LPDDR4/4x/5/5x PHY
    • Supports JEDEC SDRAM standards including LPDDR4 (1.1V), LPDDR4x (0.6V), LPDDR5/5x (0.5V)
    • Supports data rates up to 4,266 Mbps LPDDR4/LPDDR5 and up to 8,533 Mbps LPDDR5x
    • Support for 16, 32 and 64-bit operation
    Block Diagram -- LPDDR4/4x/5/5x PHY
  • TSMC CLN7FF HBM3 PHY
    • IGAHBMX03A is a HBM3 (High Bandwidth Memory) PHY IP compliant to the JEDEC HBM3 DRAM Specification Rev 0.95.
    • Built on TSMC 7nm process node, it supports data rate up to 7200 Mbps per data pin with DFI 1:4 clock frequency ratio (controller clock : WCK = 1:4).
    Block Diagram -- TSMC CLN7FF HBM3 PHY
  • USB3.1 transceiver IP with PMA and PCS layer
    • Data rate for Gen 1 physical layer is 5Gbps
    • Data rate for Gen 2 physical layer is 10Gbps
    • 4 Channel per Quad
    • Shared high performance LC tank PLL
    Block Diagram -- USB3.1 transceiver IP with PMA and PCS layer
  • JESD204B/204C IP with PHY and MAC layer
    • X4/X8 Lane Mode, support up to 25Gbps (per lane)
    • Shared common PLL based architecture
    • Digitally-control-impedance termination resistors and On-chip resistance calibration
    • Configurable TX output differential voltage swing
    Block Diagram -- JESD204B/204C IP with PHY and MAC layer
  • Rapid IO 4.0/3.1/2.2 PHY
    • 4 Channel per Quad
    • Shared Quad common PLL architecture
    • Digitally-control-impedance termination resistors
    • Configurable TX output differential voltage swing
    Block Diagram -- Rapid IO 4.0/3.1/2.2 PHY
  • 25/28/32G Combo SerDes
    • 4 Channels per Quad
    • Data rate up to 25/28/32Gbps
    • Shared Quad LC-PLL for high performance
    • Independent Ring-PLL of each channel for clock flexibility
    Block Diagram -- 25/28/32G Combo SerDes
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Semiconductor IP