BIST IP
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eFlash BIST IP
- The BIST can realize all eFlash testing items, covering UMC’s 40nm and 55nm processes, as well as SST’s 0.11um and 0.18um processes, and customized embedded eFlash IP wafer software testing and final testing.
- The BIST features a flexible serial interface, reducing the need for IC test pins and increasing testing flexibility.
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A memory BIST solution which has been optimized for Dolphin memories
- + Analyze RTL design or netlist to identify memories
- + Plan MBIST engines
- + Insert into RTL design or netlist / Top level hookup to JTAG
- + Verify stand-alone/ Verify partition level / Verify top level
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DDR3 and DDR4 Controller and PHY on TSMC 12nm
- This DDR3/4 IP combo solution presented, is meticulously designed for high performance and low power consumption, utilizing sophisticated architecture and advanced technology.
- Fabricated in TSMC’s 12nm CMOS process, this solution includes both controller and PHY IPs, providing comprehensive support for DDR3 and DDR4 memory interfaces.
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HBM4E PHY and controller
- Advanced clocking architecture minimizes clock jitter
- DFI PHY Independent Mode for initialization and training
- IEEE 1500 interface, memory BIST feature, and loop-back function
- Supports lane repair
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TSMC CLN3FFP HBM4 PHY
- IGAHBMZ03A is a High Bandwidth Memory 4 Physical Layer (HBM4 PHY) that is compliant with JEDEC HBM4 DRAM Specification JESD270-4.
- Fabricated in the TSMC 3 nm Advanced process node (N3P), it supports the data rate up to 12 Gbps per data pin in the DDR PHY Interface (DFI)-like 1:4 clock frequency ratio (HBM4 controller clock: WDQS = 1:4).
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ONFI 5.0 NAND Flash Controller IP Compliant to JEDEC
- The NAND flash controller IP provides easy, reliable access to an off-chip NAND flash. It supports all modes of the Open NAND Flash Interface (ONFI) Specification, revision 5.0, release candidate 0.5, dated 1 March 2021.
- It is backwards compatible, supporting the Single Data Rate (asynchronous) mode, the double data rate moves NV-DDR, NV-DDR2, and NVDDR3, to include the latest NV-LPDDR4 recently introduced in the latest revision.
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ONFI 4.2 NAND Flash Software Driver
- The NAND Flash Controller IP Core is a full-featured, easy to use, synthesizable core, easily integrated into any SoC or FPGA development. Designed to support SLC, MLC and TLC flash memories, it is flexible in use and easy in implementation.
- The controller works with any suitable NAND Flash memory device up to 1024Gb from leading memory providers – Micron, Samsung, Toshiba and Hynix.
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ONFI 4.2 NAND Flash Controller & PHY IP Compliant to JEDEC
- The NAND Flash Controller IP Core is a full-featured, easy to use, synthesizable core, easily integrated into any SoC or FPGA development.
- Designed to support SLC, MLC and TLC flash memories, it is flexible in use and easy in implementation. The controller works with any suitable NAND Flash memory device up to 1024Gb from leading memory providers – Micron, Samsung, Toshiba and Hynix.
