Bist IP

The NAND flash controller IP provides easy, reliable access to an off-chip NAND flash. It supports all modes of the Open NAND Flash Interface (ONFI) Specification, revision 5.0, release candidate 0.5, dated 1 March 2021.
It is backwards compatible, supporting the Single Data Rate (asynchronous) mode, the double data rate moves NV-DDR, NV-DDR2, and NVDDR3, to include the latest NV-LPDDR4 recently introduced in the latest revision.

The NAND Flash Controller IP Core is a full-featured, easy to use, synthesizable core, easily integrated into any SoC or FPGA development. Designed to support SLC, MLC and TLC flash memories, it is flexible in use and easy in implementation.
The controller works with any suitable NAND Flash memory device up to 1024Gb from leading memory providers – Micron, Samsung, Toshiba and Hynix.

The NAND Flash Controller IP Core is a full-featured, easy to use, synthesizable core, easily integrated into any SoC or FPGA development.
Designed to support SLC, MLC and TLC flash memories, it is flexible in use and easy in implementation. The controller works with any suitable NAND Flash memory device up to 1024Gb from leading memory providers – Micron, Samsung, Toshiba and Hynix.

The MIPI C/D-PHY combo IP is a high-frequency low-power, low cost, physical layer compliant with the MIPI^® Alliance Standard for C-PHY and D-PHY.
The PHY can be configured as a MIPI Master or MIPI Slave, supporting camera interface CSI-2 v1.2 or display interface DSI v1.3 applications in the D-PHY mode. It also supports camera interface CSI-2 v1.3 and display interface DSI-2 v1.0 applications in the C-PHY mode.

The C-PHY configuration consists of up to three lane modules and is based on 3-Phase symbol encoding technology, delivering 2.28 bits per symbol over three-wire trios and targeting a maximum rate of 2.5 Gsps, 5.7Gbps.
The C-PHY is partitioned into a digital module – CIL (Control and Interface Logic) and a mixed-signal module. The PHY IP is provided as a combination of soft IP views (RTL, and STA Constraints) for the digital module, and hard IP views (GDSII/CDL/LEF/LIB) for the mixed-signal module.

Compliant with the UCIe specification (2.0 & 1.1)
Flexible Structure, easy to customize (Pre-hardened PHY tuned to Customer Spec, PHY + Adapter Layer, PHY + Adapter Layer + Customized Protocol Layer)
Supports the CXS/AXI using the streaming package (AXI Interface bandwidth up to 89%)

The MIPI D-PHY + DSI/CSI Controller IP is a versatile solution designed for high-speed data transmission in mobile and multimedia applications
It supports MIPI D-PHY 2.0 standards
The IP features a compact design with built-in I/O and ESD protection, optimized for robust performance and low power consumption
It enables seamless connectivity with D-PHY based sensors, making it ideal for SoCs in consumer electronics, automotive, and IoT devices

The DP/eDP IP is designed for transmitting or receiving video and audio signals between the video source devices and display devices
It is fully compliant with DP1.4 and eDP1.4 specifications
The IP provides both PHY and controller solutions, offering a reliable implementation for DisplayPort and embedded DisplayPort interfaces that can be seamlessly integrated in the SoCs used in multimedia devices

BIST IP