BIST IP
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1,018
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eFlash BIST IP
- The BIST can realize all eFlash testing items, covering UMC’s 40nm and 55nm processes, as well as SST’s 0.11um and 0.18um processes, and customized embedded eFlash IP wafer software testing and final testing.
- The BIST features a flexible serial interface, reducing the need for IC test pins and increasing testing flexibility.
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A memory BIST solution which has been optimized for Dolphin memories
- + Analyze RTL design or netlist to identify memories
- + Plan MBIST engines
- + Insert into RTL design or netlist / Top level hookup to JTAG
- + Verify stand-alone/ Verify partition level / Verify top level
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DDR4/LPDDR4 PHY Interface
- The DDR PHY IP is a combination of hard macro, I/O Pad and synthesizable RTL to provide a physical interface to JEDEC standard DDR3/DDR4 SDRAM memories.
- The synthesizable RTL (ddr_phy_top) provides control functions such as initialization, SDRAM interface training, impedance calibration and programmable configuration controls.
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xSPI + eMMC Combo PHY IP
- This IP integrates both xSPI (Expanded Serial Peripheral Interface) and eMMC 5.1 PHY (Physical Layer) into a single unified solution, enabling support for two distinct memory protocols within the same IP.
- By combining the PHY layers for both interfaces, the design simplifies system integration, reduces area and pin count, and enhances design flexibility for SoCs that require both boot and high-speed storage functionality.
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SD4.x UHSII
- Fully compliant with UHSII specification Ver. 4.x
- Bidirectional receiver/transmitter (2 channels) supporting both full and half duplex modes
- Supports data rates from 390Mbps to 1.56Gbps/ch
- RCLK frequency: 26 to 56MHz
- Built-in PLL and clock recovery
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DDR3 and DDR4 Controller and PHY on TSMC 12nm
- This DDR3/4 IP combo solution presented, is meticulously designed for high performance and low power consumption, utilizing sophisticated architecture and advanced technology.
- Fabricated in TSMC’s 12nm CMOS process, this solution includes both controller and PHY IPs, providing comprehensive support for DDR3 and DDR4 memory interfaces.
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HBM4E PHY and controller
- Advanced clocking architecture minimizes clock jitter
- DFI PHY Independent Mode for initialization and training
- IEEE 1500 interface, memory BIST feature, and loop-back function
- Supports lane repair
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TSMC CLN3FFP HBM4 PHY
- IGAHBMZ03A is a High Bandwidth Memory 4 Physical Layer (HBM4 PHY) that is compliant with JEDEC HBM4 DRAM Specification JESD270-4.
- Fabricated in the TSMC 3 nm Advanced process node (N3P), it supports the data rate up to 12 Gbps per data pin in the DDR PHY Interface (DFI)-like 1:4 clock frequency ratio (HBM4 controller clock: WDQS = 1:4).
