Timing Optimization Technique Using Useful Skew in 5nm Technology Node
February 9, 2025
Semiconductor IP Articles
Securing a 4G-connected Smart Meter Gateway with CHERI
February 7, 2025
Interstellar: Fully Partitioned and Efficient Security Monitoring Hardware Near a Processor Core for Protecting Systems against Attacks on Privileged Software
February 6, 2025
Bigger Chips, More IPs, and Mounting Challenges in Addressing the Growing Complexity of SoC Design
February 5, 2025
Infinite-ISP: An Open Source Hardware Image Signal Processor Platform for all Imaging Needs
February 4, 2025
Leveraging ASIC AI Chips for Homomorphic Encryption
January 31, 2025
A novel 3D buffer memory for AI and machine learning
January 27, 2025
Novel Trade-offs in 5 nm FinFET SRAM Arrays at Extremely Low Temperatures
January 27, 2025
Assessing Design Space for the Device-Circuit Codesign of Nonvolatile Memory-Based Compute-in-Memory Accelerators
January 27, 2025
The SoC design: What’s next for NoCs?
January 24, 2025
Streamlining SoC Design with IDS-Integrate™
January 23, 2025
Linearity Analysis of Source-Degenerated Differential Pairs for Wireline Applications
January 22, 2025
How Ultra Ethernet And UALink Enable High-Performance, Scalable AI Networks
January 20, 2025
Expanding the Horizon of System Monitoring with the Arm SMCF
January 20, 2025
Monolithic 3D FPGAs Utilizing Back-End-of-Line Configuration Memories
January 19, 2025
Reimagining AI Infrastructure: The Power of Converged Back-end Networks
January 15, 2025
40G UCIe IP Advantages for AI Applications
January 13, 2025
Recent progress in spin-orbit torque magnetic random-access memory
January 13, 2025
What is JESD204C? A quick glance at the standard
January 9, 2025
Open-Source Design of Heterogeneous SoCs for AI Acceleration: the PULP Platform Experience
January 9, 2025
