Novel Trade-offs in 5 nm FinFET SRAM Arrays at Extremely Low Temperatures

By Shivendra Singh Parihar, Girish Pahwa, Baker Mohammad, Yogesh Singh Chauhan, Hussam Amrouch

Abstract:

Complementary metal–oxide–semiconductor (CMOS)-based computing promises drastic improvement in performance at extremely low temperatures (e.g., 77 K, 10 K). The field of extremely low temperature CMOS-environment-based computing holds the promise of delivering remarkable enhancements in both performance and power consumption. Static random access memory (SRAM) plays a major role in determining the performance and efficiency of any processor due to its superior performance and density. This work aims to reveal how extremely low temperature operations profoundly impact the existing well-known tradeoffs in SRAM-based memory arrays. To accomplish this, first, we measure and model the 5 nm fin field-effect transistors characteristics over a wide temperature range from 300 K down to 10 K. Next, we develop a framework to perform simulations on the SRAM array by varying the number of rows and columns for examining the influence of leakage current (I_leak) and parasitic effects of bit line (BL) and word line (WL) on the size and performance of the SRAM array under extremely low temperatures. For a comprehensive analysis, we further investigated the maximum attainable array size, extending our study down to 10 K, utilizing three distinct cell types. With the help of SRAM array simulations, we reveal that the maximum array size at extremely low temperatures is limited by WL parasitics instead of I_leak, and the performance of the SRAM is governed by BL and WL parasitics. In addition, we elucidate the influence of transistor threshold voltage (V_TH) engineering on the optimization of the SRAM array at extremely low temperature environments.

Introduction

Cryogenic complementary metal–oxide–semiconductor (CMOS) technology has been of researchers' interest since 1960s due to improved transistors' performance at extremely low temperatures, i.e., higher on-state current (I_ON) and lower off-state current (I_OFF). CMOS-based electronic circuitry for deep-space applications has always been in demand. The emergence of novel applications has further resulted in significant interest in CMOS-based cryogenic electronics during the last decade. Recently, there have been several proposals from industries, such as IBM, Kioxia, and ARM, on designing memories and computers for extremely low temperature operations. The invention of newer technologies, such as exascale computing, control circuitry for quantum computers (QCs), silicon-based QCs, etc., resulted in huge demand for cryogenic processors and memories. Besides these applications, circuits that operate at extreme temperatures are also utilized in medical engineering to design medical equipment, e.g., magnetic resonance imaging. In QCs, a large number of quantum algorithms are utilized to control and manipulate the qubits, necessitating the high-capacity memories to store these programs. Furthermore, a large memory is needed to have a fault-tolerant quantum computing system, where the static random access memory (SRAM) can be employed as a weight element for quantum error correction circuitry. Similarly, the computing cores in high-performance (HP) computers continuously access the on-chip SRAM-based cache memories operating at extremely low temperatures.

SRAM occupies a large portion of the chip in any processor and plays a crucial role in dictating the overall performance and energy efficiency of the entire processing unit. With each newer generation of CMOS technology node, I_OFF and wire resistance also increase apart from the increase in I_ON and density. Increasing I_OFF and wire resistance at an advanced technology node hinders the development of large memory arrays due to increased static power dissipation and latency. Typically, large arrays are subdivided into smaller subarrays to build large-capacity memory, which comes with a high cost in the area and power consumption because of the extra peripheral circuits.

A conventional SRAM array has millions of SRAM bit cells, as well as peripheral hardware circuitry, to facilitate the read and write operations in the memory. In the SRAM array, all the cells placed in each row share a single word line (WL), and all cells in each column share a single bit-line (BL) pair [BL and bit line bar (BLB)]. Fig. 1(a) shows the circuit utilized to generate different signals (e.g., precharge enable, WL signal, write enable, and sense enable) from the clock signal in this work. In our SRAM array implementation, each column in the array has its own peripheral circuits [see Fig. 1(b)], e.g., a precharge circuit to precharge the BL pair, sense amplifier to differentiate the voltage difference on BL and BLB during the read operation, write a driver for writing into the cells, and output latch.

There have been multiple reports on the cryogenic characterization of SRAM using both experiments and simulations [14], [19], [20], [21], [22], [23], [24], [25], [26], [27], [28]. However, all these studies only report the advantage of operating at cryogenic temperatures and are limited to evaluating a fixed array size. As I_OFF at 77 and 10 K decreases by four to five orders [29], the primary constraint of building a large memory array, i.e., leakage current (I_leak), will not be a major concern and will lead to novel design tradeoffs for memory optimization. The lower I_leak at extremely low temperatures will help keep more bit cells in columns compared to arrays designed for 300 K. A smaller wire resistance at extremely low temperatures [30], [31], [32] can also help upscale the memory array size. Smaller wire resistance at extremely low temperatures may further help upscale the clock frequency of the computers under a constant power budget [33]. Hence, in this work, with the help of calibrated cryogenic-aware compact model-based simulations, we explore the SRAM array optimization for extremely low temperature operations.

Distinction from state of the art: Existing works on SRAM operating at extremely low temperatures are mainly focused on the characterization of the following:

1. noise resiliency, power consumption, retention time, and performance during read-and-write operation of off-the-shelf SRAM in a constant array size;
2. the impact of transistors' work function engineering on SRAM performance of fixed array size;
3. superconducting-CMOS hybrid 8T-SRAM with a constant array size operating at 1 GHz.

A detailed literature search on the cryogenic behavior of SRAM in a constant array is included in the Appendixes. The maximum array size, the impact of parasitic on WL and BL voltages, the impact of I_leak on bit delay (T_ΔBL), etc., at extremely low temperatures is still unexplored, where T_ΔBL is the time spent between WL activation to the time SRAM cell takes to produce a 100-mV difference between BL and BLB during the read operation. Hence, in this work, we explore the maximum array size possible to design without any assist scheme using commercially available state-of-the-art 5 nm fin field-effect transistor (FinFET) technology.

Our novel contributions within this article are as follows.

1. For the first time, we unveil the novel enhanced tradeoffs in SRAM arrays that extremely low temperature brings, using 5 nm FinFETs.
2. We demonstrate the deleterious impact of WL and BL parasitic on read and write operations of SRAM at extremely low temperatures.
3. We reveal the necessity of memory array optimization for cryogenic applications and present the maximum array size possible for a constant frequency and supply voltage at extremely low temperatures.
4. We investigate the role of transistors' threshold voltage engineering on cryogenic-specific SRAM array optimization.

Key insights which this work brings are as follows.

1. I_leak does not limit the maximum array size at extremely low temperature; instead, WL parasitics are the ones that hinder the array scaling.
2. T_ΔBL is primarily governed by BL and WL parasitics at extremely low temperatures.
3. I_leak of any column must not exceed 25% of the read current (I_read) of individual cells in an array with 512 rows and working at a clock frequency of 2 GHz.
4. Operations at extremely low temperatures help to achieve an array size of ∼ 1.35× compared to 300 K when designed using the high-density cell (HDC).

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