Frank Schirrmeister on Synopsys’ Upgraded Hardware-Assisted Validation Platforms.
Designing chips is hard, but validating them can be harder still. Synopsys has upgraded their Hardware-Assisted Validation platforms, and Karl Freund, Founder and Principle Analyst, Cambrian-AI Research spoke with Frank Schirrmeister Executive Director, Strategic Programs, System Solutions at Synopsys to understand what was announced.
Related Semiconductor IP
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
- 10-bit Pipeline ADC - Tower 180 nm
- NoC Verification IP
- Simulation VIP for Ethernet UEC
- Automotive Grade PLLs, Oscillators, SerDes PMAs, LVDS/CML IP
Related Videos
- RISC-V Design Innovations with Custom Extensions
- Synopsys 800G MAC, PCS and PHY IP Interop with Switches and Optical Links at ECOC '24
- CES 2025: Video Interview with Ceva's Amir Panush
- CES 2025: Video Interview with EdgeCortix’s CEO
Latest Videos
- How UCIe 3.0 Redefining Chiplet Architecture: From Protocol to Platform
- Teradyne Testimonial: Silicon Creations' 16nm SerDes Enables Fastest TTM and Most Cost-Effective Teradyne ASIC Development To-Date
- Webinar: Unpacking System Performance – Supercharge Your Systems with Lossless Compression IPs
- Arm: From Cloud-to-Car Architecture
- High Performance RISC-V is here!