RISC-V Design Innovations with Custom Extensions
Andes and Synopsys present a ‘software first’ design flow using virtual platforms/prototypes allows RISC-V developers to explore new hardware configuration options with application SW workloads and full OS support.
Related Semiconductor IP
- HBM4 PHY IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- HBM4 Controller IP
- IPSEC AES-256-GCM (Standalone IPsec)
- Parameterizable compact BCH codec
Related Videos
- How to design robust SoC with ESD and power management IP
- Architecture Exploration of SoC with Arm IP using VisualSim Architect
- Secure RISC-V Processor for Root of Trust
- LLM Inference on RISC-V Embedded CPUs
Latest Videos
- How UCIe 3.0 Redefining Chiplet Architecture: From Protocol to Platform
- Teradyne Testimonial: Silicon Creations' 16nm SerDes Enables Fastest TTM and Most Cost-Effective Teradyne ASIC Development To-Date
- Webinar: Unpacking System Performance – Supercharge Your Systems with Lossless Compression IPs
- Arm: From Cloud-to-Car Architecture
- High Performance RISC-V is here!