RISC-V Design Innovations with Custom Extensions
Andes and Synopsys present a ‘software first’ design flow using virtual platforms/prototypes allows RISC-V developers to explore new hardware configuration options with application SW workloads and full OS support.
Related Semiconductor IP
- USB 20Gbps Device Controller
- AGILEX 7 R-Tile Gen5 NVMe Host IP
- 100G PAM4 Serdes PHY - 14nm
- Bluetooth Low Energy Subsystem IP
- Multi-core capable 64-bit RISC-V CPU with vector extensions
Related Videos
- How to design robust SoC with ESD and power management IP
- Architecture Exploration of SoC with Arm IP using VisualSim Architect
- Secure RISC-V Processor for Root of Trust
- LLM Inference on RISC-V Embedded CPUs