TSMC implements MoSys' new low-power 1T-SRAM for 0.13-micron process

TSMC implements MoSys' new low-power 1T-SRAM for 0.13-micron process
By Semiconductor Business News
November 21, 2001 (6:26 p.m. EST)
URL: http://www.eetimes.com/story/OEG20011121S0109

SUNNYVALE, CALIF. -- MoSys Inc. here said silicon foundry giant Taiwan Semiconductor Manufacturing Co. Ltd. has successfully implemented the company's 1T-SRAM-M technology for second-generation one-transistor memory cells used in low-power mobile systems applications.

Last spring, MoSys announced it was teaming up with TSMC to create new low-power and double-density derivatives of 1T-SRAM cells for 0.13-micron foundry processes. As part of that partnership, TSMC inked a series of new licensing pacts with MoSys (see April 9 story).

The second-generation 1T-SRAM-M technology retains data with a standby current of just 10 microamps per megabit or less when fabricated in TSMC's 0.13-micron process, according to MoSys.

The 1T-SRAM has demonstrated superior soft-error-rate (SER) reliability than six-transistor SRAM cells, starting at the 0.15-micron process node, said Fu -Chieh Hsu, chief executive officer of MoSys. "Our reliability figures-of-merit are now orders of magnitude better on the 0.13-micron process node and beyond," he added.

MoSys said the traditional six-transistor SRAM suffers from the fundamental CMOS scaling limit of sub-threshold voltage, which must be a small fraction of the supply voltage. As advanced logic processes progress to 0.13-micron and below, the supply voltage is reduced to 1.2 V or lower. To maintain device performance, thethreshold voltages are also lowered, which causes all transistors to leak even when there is no circuit switching, said the company. The problem grows worse when large embedded memories are used in system-on-chip designs, MoSys said.

In addition to announcing the implementation of the new low-power cell, MoSys said its 1T-SRAM technology has been verified on multiple versions of TSMC¹s 0.13-micron standard and triple-oxide logic processes. TSMC in Hsinchu, Taiwan, is now ready to accept foundry customers' tapeouts uti lizing these 0.13-micron triple-oxide logic processes.

MoSys and TSMC also announced continuation of verification and testing of 1T-SRAM memory cells for 0.10-micron processes.