Analog Bits to Demonstrate Numerous Test Chips Including Portfolio of Power Management and Embedded Clocking and High Accuracy Sensor IP in TSMC N3P Process at TSMC 2024 North America Technology Symposium
Highlights of Three Demo Stations
- New LDO, High accuracy PVT Sensors, High Performance Clocks, Droop Detectors, and more in N3P
- Patented Pinless PLL’s and Sensors in N3, N4 and N5
- Automotive Grade SERDES, PLL’s, Sensors, and IOs in N5A
Sunnyvale, CA, April 22, 2024 - Analog Bits (www.analogbits.com), the industry’s leading provider of low-power mixed-signal IP (Intellectual Property) solutions will be demonstrating newest LDO IP, Power supply droop detectors, Embedded Clock LC PLL’s, etc. in TSMC N3P process at their booth at the TSMC 2024 North America Technology Symposium in Santa Clara Convention Center, Santa Clara, California. This demonstration is showcasing Analog Bits’ industry leading portfolio of Mixed Signal IP in advanced 3nm, 4nm, 5nm, and Automotive processes.
“Analog Bits continuous customer focus and passion for innovating IP’s to solve 3nm and 2nm design problems has enabled us to rapidly innovate and deploy IP’s to lower system costs and improve performance,” said Mahesh Tirupattur, Executive Vice President at Analog Bits. “With SoC’s going multicores, managing power into the cores is imperative. We have designed novel LDO macros that can be easily scaled, arrayed and shared adjacent to CPU cores and simultaneously monitoring power supply health with our detector macros allowing customers to balance power real time. It is like PLL’s that maintain clocking stability we have are now able to offer IP’s to maintain power integrity in real time. Come and see our demos.”
When: April 24th, 2024
Location: Santa Clara Convention Center, Booth #716
Resources
About Analog Bits
Founded in 1995, Analog Bits, Inc. (www.analogbits.com), is the leading supplier of mixed-signal IP with a reputation for easy and reliable integration into advanced SOCs.
Our products include precision clocking macros, Sensors, programmable interconnect solutions such as multi-protocol SERDES and programmable I/O’s. With billions of IP cores fabricated in customer silicon, from 0.35 micron to 3nm processes, Analog Bits has an outstanding heritage of "first-time-working” with foundries and IDMs.
Related Semiconductor IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
- High Speed Ethernet 2/4/8-Lane 200G/400G PCS
Related News
- Credo at TSMC 2024 North America Technology Symposium
- Analog Bits to Demonstrate Pinless PLL and Sensor IP's in TSMC N5 Process at TSMC 2022 North America Technology Symposium
- Analog Bits to Demonstrate Working Silicon on TSMC N3E Process at TSMC 2023 North America Technology Symposium
- Analog Bits to Demonstrate Automotive Grade IP's Including a Novel High Accuracy Sensor at TSMC 2023 North America Open Innovation Platform Ecosystem Forum
Latest News
- PCI-SIG’s Al Yanes on PCIe 7.0, HPC, and the Future of Interconnects
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- Cadence Unveils Arm-Based System Chiplet
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy