TransEDA enhances verification environment <!-- verification -->

TransEDA enhances verification environment
By Michael Santarini, EE Times
January 30, 2002 (4:38 a.m. EST)
URL: http://www.eetimes.com/story/OEG20020129S0026

SAN MATEO, Calif. — TransEDA plc has added the VN-Control application-specific test-automation tool and upgraded two other tools in the latest revision of its Verification Navigator integrated design-verification environment.

Verification Navigator is a common user interface, or "verification cockpit," from which verification engineers can organize and control four standalone tools from TransEDA: the new VN-Control, VN-Optimize, VN-Cover and VN-Check. TransEDA has enhanced both the VN-Cover code-coverage analysis and VN-Check configurable HDL checker tools in version 2002.1.

Verification Navigator is a no-charge feature that TransEDA includes with the purchase of any one of these tools.

VN-Cover now has a finite-state-machine path metric and support for 64-bit simulation platforms, said Tom Borgstrom, vice president of marketing at TransEDA. The previous version included metrics for visited-state coverage and arc coverage that allowed users to determine whether or not the tool had inspected every state and transition between states (arc). Borgstrom said the new FSM path metric goes further, allowing users to view finite-state-machine functionality, creating an abstract view of the FSM functionality in terms of "cycles," "supercylces" and "links."

"Arc and visited-state coverage are relatively simple metrics and they don't really relate to the intended functionality of the state machine," said Borgstrom. "With the FSM path metric, we look at sequences of transmissions. These paths closely relate to how the FSMs operate."

The company has also made VN-Cover compatible with the 64-bit version of Model Technologies' ModelSim simulator.

The 2002.1 release of VN-Check, meanwhile, boasts enhanced run-time and memory performance as well as dual-language (mixed Verilog and VHDL) and Verilog IEEE-1364-2001 language support. This feature allows users to organize checks by rules sets such as finite state machines, design-for-test or design-for-reuse.

"Dual-language support allows users to perform HDL checking on both Verilog and VHDL blocks in a design in one pass," said Borgstrom, who noted the previous version required a run of VN-Check for each language.

VN-Check now includes the VN-Check CRC custom-rule creation utility, which the company previously offered as a separate option. Borgstrom said the feature allows users to write up their own custom rules sets in Perl or Java. "We provide APIs [application programming interfaces] for Perl and Java," said Borgstrom. "The CRC provides documentation to the API and we will automatically develop the wrapper for these custom rules to be coded into."

TransEDA has also doubled VN-Check's performance and reduced its memory signature by 10 to 50 percent, depending on the rules selected for a run.

VN-Cover and VN-Check start at $20,000 each for a perpetual license. VN-Control starts at $5,000 for an annua l subscription license.