TransEDA Tools Speed Verification Process for Paxonet Communications’ New Optical Networking Products
Company Standardizes on VN-Cover As Part of IP Reuse Methodology
LOS GATOS, Calif. — April 15, 2002 — TransEDA® PLC, the leader in ready-to-use verification solutions for electronic designs, announced that Paxonet Communications standardized on TransEDA’s VN-Cover™ coverage analysis solution as part of its verification methodology for its new optical networking products. Paxonet is a fabless application specific standard product (ASSP) company that provides solutions for next generation optical networks.
"With VN-Cover, we can really increase our confidence that our designs are fully verified," said Simon Matthews, chief engineer, Paxonet Communications. "Although we used the basic coverage analysis capabilities provided with our simulator, we found it insufficient for rapid improvement of our coverage. We typically shoot for 95 percent comprehensive coverage in our designs, and are able to meet close to 100 percent for statement and branch. TransEDA goes beyond this to provide a complete set of coverage metrics in an easy-to-use environment that helps us speed coverage closure and design release."
Paxonet recently used TransEDA’s VN-Cover to verify its Chopper product—an integrated, single-chip solution for performing classification and policing of packets and cells in a network. With two million gates, the product required extensive test benches to be written. The company also successfully used the product for validation of test benches in its 10G Ethernet MAC core. Paxonet used VN-Cover during simulations run at the module level of the designs rather than the chip level. The company finds this methodology speeds the overall verification process. IP validated at the module level can also be reused in future designs, cutting design time for those projects.
"Using TransEDA’s products on our new 10G MAC core and Chopper product proved to be a good decision, as we found a few bugs we had not previously discovered," said Pramod Phadke, general manager - engineering, Paxonet. "VN-Cover gives us an objective way to validate our test scripts—a process that was previously largely manual. In order to gain full confidence in our verification effort, we had to spend many more man-hours. Because we use VN-Cover at the module level, we are able to detect and correct bugs up front. During this process, VN-Cover helps us especially in identifying corner cases that we may have overlooked in our initial test scripts. The end result is faster simulation, higher productivity, and pre-verified IP that speeds the completion of future designs."
Contacts:
TransEDA - Tom Borgstrom, (408) 907-2225; tom.borgstrom@transeda.com.
PentaCom – Sharon Graves, +44 1242 525205, sharon.graves@pentacomagency.com.
Armstrong Kendall, Inc. – Jen Bernier, (408) 975-9863, jen@akipr.com.
Related Semiconductor IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
- High Speed Ethernet 2/4/8-Lane 200G/400G PCS
Related News
- Xilinx Showcases Future of Optical Networking with Breakthrough Technology and Products at OFC 2018
- Acacia Communications Adopts Cadence Palladium Z1 Enterprise Emulation Platform to Accelerate Optical Networking Development
- Xilinx and Paxonet Communications announce industry's first programmable G.709-based Optical Transport Network (OTN) solutions
- Micron Boosts DDR3 Offering With 2Gb and 4Gb, 1GHz/DDR3-2133, Delivering Power Efficiency and Speed for High-Performance Networking and Graphics Segments
Latest News
- HPC customer engages Sondrel for high end chip design
- PCI-SIG’s Al Yanes on PCIe 7.0, HPC, and the Future of Interconnects
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- Cadence Unveils Arm-Based System Chiplet
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers