Syntacore upgrades its SCR RISC-V IP: Packed-SIMD, Zicond and Zimop Extensions

January 13, 2026 -- Syntacore, a RISC-V IP and SW tools specialist, upgrades its SCR3, SCR4 and SCR5 cores with support for Packed-SIMD (P), Integer Conditional Operations (Zicond), and May-Be-Operations (Zimop) extensions. The extensions are fully compliant with the most recent RISC-V specifications:

• “Packed-SIMD” Extension for DSP Operations
• "Zicond" Extension for Integer Conditional Operations
• "Zimop" Extension for May-Be-Operations

The Packed-SIMD extension includes a set of specialized instructions that improve the efficiency of DSP algorithms by processing data in packets, reducing the overall number of operations and significantly accelerating computations in a wide spectrum of workloads – sensor fusion, industrial controllers, image/audio processing and others. Internal tests show a DSP performance increase by a factor of multiple in a wide range of scenarios.

The Zicond and Zimop extensions optimize critical code sections (simple loops and conditions) by eliminating conditional jumps. Their support allows to:

• Zicond: replace branches with conditional data selection operations between registers, eliminating mispredictions and associated pipeline stalls.
• Zimop: efficiently perform conditional operations on immediate operands (constants), reducing the number of instructions.

The enhancement results in improved performance and more deterministic execution times in DSP tasks, control algorithms, cryptography, and data compression.

Explore RISC-V IP:

• High-performance Linux-capable application core with a 12-stage dual-issue out-of-order pipeline, a VPU, cache coherency, and a hypervisor
• High-performance microcontroller core with a 12-stage dual-issue out-of-order pipeline and a high performance FPU
• High-performance Linux-capable application core with a 12-stage dual-issue out-of-order pipeline, and cache coherency
• Efficient microcontroller core with a 5-stage in-order pipeline, privilege modes, an FPU, an MPU, L1 and L2 caches
• Open-source compact microcontroller core with a 4-stage in-order pipeline for deeply embedded applications

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