Spec eyes 'plug and play' test for virtual components <!-- verification -->

Spec eyes 'plug and play' test for virtual components
By EE Times
September 4, 2001 (10:42 a.m. EST)
URL: http://www.eetimes.com/story/OEG20010904S0034

The Virtual Socket Interface Alliance (VSIA) this week will release a standard that defines structures for test access to individual virtual components (VCs) embedded on a system-on-chip.

The Test Access Architecture Standard Version 1.0 will serve as a testing ground for the upcoming IEEE P1500 standard and will be compatible with the IEEE document once that standard is released in the next 18 months.

Multiple-core reuse was among the largest drivers of the standardization work, according to R. Chandramouli, a product line manager in Synopsys' Test Automation Group and a member of VSIA's Manufacturing Related Test Group.

As multimillion-gate designs become more commonplace, gaining access to myriad integrated cores for the purposes of testing becomes more difficult. "A good example is the cell phone market, which packs so much functionality together, like fax and e-mail and things in the computer domain," Chandramouli said. "T hese systems are on very short design cycles. You've got to make sure you can manufacture them quickly, with quality and in high volume. To do that, you need to get in and out of the components, have access to them and test them."

A step toward virtual-component "plug and play" test, the VSIA standard defines the architecture and a set of rules and recommendations for accessing the test structures of embedded VCs. It describes the various input and output wrapper registers for testing individual virtual components and includes associated test logic rules and recommendations.

"We went through multiple existing test methodologies, tweaked them and came up with a reasonable way to access cores," Chandramouli said. "It's somewhat akin to boundary scan, where you put a wrapper around the core and then a small controller to control what goes in and out."

The wrappers, a type of design-for-test technology, are logic structures around the intellectual property that support both isolation and access into and out of the IP during testing. The standard begins by defining a set of rules specifying various test modes required for testing embedded VCs. Next is a description of the basic architecture for VC test access, an associated set of interface signals for test access, and specification of the architectural requirements in terms of rules and permissions.

The VSIA hopes to present early-adopter case studies of the standard to the IEEE for tweaking of the P1500 standard. "Our standard will be upwardly compatible with P1500, though you might have to put a small layer around it," Chandramouli said. "But the IEEE typically takes a longer cycle time to get standards out, and there was a big industry clamor for some kind of standardization."

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Wind River Systems co-founder and chairman Jerry Fiddler has joined the board of directors at configurable processor core vendor Tensilica Inc. "I have followed Tensilica closely over the past three years," Fiddler said in a prepared s tatement. "They're well-positioned at a key point in the new trend toward dynamic silicon."

Fiddler also sits on the board of Axis Systems.

- Edited by Michael Santarini, with a contribution from Jerry Ascierto.