Simplifying the Analog and Mixed-Signal IC Design Process
By Maurizio Di Paolo Emilio, EEWeb (June 14, 2023)
Analog and mixed-signal (AMS) circuit design typically involves designing components like amplifiers, filters and data converters, which can be complex and time-consuming, often requiring manual design expertise and iterations.
This article is focused on the revolutionary approach to the design of AMS circuits developed by Agile Analog. This U.K.-based semiconductor company simplifies and accelerates this process with its scalable platform.
By automating parts of the design process, Agile Analog makes the analog design more accessible to a broader range of engineers, including those without extensive expertise in analog circuit design. The main goal is to enable faster and more reliable development of analog ICs, crucial for various applications, including telecommunications, automotive, consumer electronics and internet-of-things devices.
To read the full article, click here
Related Semiconductor IP
- UCIe Chiplet PHY & Controller
- MIPI D-PHY1.2 CSI/DSI TX and RX
- Low-Power ISP
- eMMC/SD/SDIO Combo IP
- DP/eDP
Related News
- Siemens delivers AI- accelerated verification for analog, mixed-signal, RF, memory, library IP and 3D IC designs in Solido Simulation Suite
- Agile Analog announces MoU to support new Southern Taiwan IC Design Industry
- Synopsys Expands the Industry's Highest Performance Hardware-Assisted Verification Portfolio to Propel Next-Generation Semiconductor and Design Innovation
- Europe takes a major step towards digital autonomy in supercomputing and AI with the launch of DARE project
Latest News
- Frontgrade Gaisler and wolfSSL Collaborate to Enhance Cybersecurity in Space Applications
- Digital Core Design Unveils DPSI5 - The Next-Generation IP Core for PSI5 Communication
- Matrox Video and intoPIX Expand Interoperable IPMX & ST 2110 Solutions with JPEG XS Innovation at NAB 2025
- HCLTech joins Samsung Advanced Foundry Ecosystem as a Design Solution Partner
- TeraSignal to Showcase Retimer-Less PCIe 6.0 over Optics Featuring Synopsys IP at OFC 2025