Tracing Samsung's Road to 14nm

Kevin Gibb, Product Line Manager, Process, TechInsights
5/12/2015 09:46 AM EDT

Samsung has lagged behind Intel in release of process nodes. Remarkably, Samsung has now shrunk the lag for its 14nm to about 6 months.

Nearly a decade ago, the future appeared to be a divide between gate-last and gate-first high-k metal gate (HKMG) transistors that were soon to be implemented in the 45nm or 32nm process nodes. Intel went with a gate-last process while the IBM Common Platform, which included Samsung, adopted a gate-first process.

The gate-first approach follows a traditional CMOS process where the gate stack is deposited and patterned before the formation of the source/drain implants. The process is somewhat more complicated in that the oxide or nitrided gate oxide is replaced with a high-k gate dielectric (for example HfO2/oxide stack) plus a thin work function (WF) metal layer is formed on top of the high-k gate dielectric. A polycide gate layer covers the work function metal to complete the gate stack.

Both the gate-first and gate-last processes require a dual-work function metallization scheme to separately tune the NMOS and PMOS transistor threshold voltages. This complicated the fabrication process for making metal gate transistors as several metal deposition and etch processes are required to form the two work function metals and the remaining gate fill.

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