Qualcomm defines format for 3-D chip stress
Rick Merritt, EETimes
9/22/2010 5:24 PM EDT
"We think industry needs to get together on this, everyone needs this enablement—we'll compete on other things," said Mark Nakamoto, a Qualcomm engineer.
To read the full article, click here
Related Semiconductor IP
- Specialized Video Processing NPU IP for SR, NR, Demosaic, AI ISP, Object Detection, Semantic Segmentation
- Ultra-Low-Power Temperature/Voltage Monitor
- Multi-channel Ultra Ethernet TSS Transform Engine
- Configurable CPU tailored precisely to your needs
- Ultra high-performance low-power ADC
Related News
- Qualcomm and Himax Technologies Jointly Announce High Resolution 3D Depth Sensing Solution
- Foundry model under stress
- GLOBALFOUNDRIES Fab 8 Adds Tools To Enable 3D Chip Stacking at 20nm and Beyond
- Chip execs see 20 nm variants, 3-D ICs ahead
Latest News
- Siemens accelerates integrated circuit design and verification with agentic AI in Questa One
- Weebit Nano achieves record half-year revenue; licenses ReRAM to Tier-1 Texas Instruments
- IObundle Releases Open-Source UART16550 Core for FPGA SoC Design
- Rapidus Secures 267.6 Billion Yen in Funding from Japan Government and Private Sector Companies
- DNP Invests in Rapidus to Support the Establishment of Mass Production for Next-Generation Semiconductors