Qualcomm defines format for 3-D chip stress
Rick Merritt, EETimes
9/22/2010 5:24 PM EDT
SAN JOSE, Calif. – Qualcomm has teamed up with Synopsys to define a new data exchange format it believes could be critical for supporting 3-D chip stacks that use through silicon vias. Qualcomm has already gotten support from at least one foundry and one chip assembler for the so-called Stress Exchange Format.
"We think industry needs to get together on this, everyone needs this enablement—we'll compete on other things," said Mark Nakamoto, a Qualcomm engineer.
To read the full article, click here
Related Semiconductor IP
- 250nA-88μA Current Reference - X-FAB XT018-0.18μm BCD-on-SOI CMOS
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
- MIPI CSI-2 CSE2 Security Module
Related News
- Qualcomm and Himax Technologies Jointly Announce High Resolution 3D Depth Sensing Solution
- Foundry model under stress
- Chip execs see 20 nm variants, 3-D ICs ahead
- 3D Graphics on Xilinx ZC702 Board
Latest News
- CAST Introduces MAC-SEC-MG IP Core for Secure 10G+ Ethernet SoC Designs
- Crypto Quantique and Attopsemi Unite PUF and I-fuse® OTP technology to Deliver Zero-Overhead Device Enrollment on FinFET Technology
- Arasan Announces immediate availability of its UFS 5.0 Host controller IP
- Bolt Graphics Completes Tape-Out of Test Chip for Its High-Performance Zeus GPU, A Major Milestone in Reducing Computing Costs By 17x
- NEO Semiconductor Demonstrates 3D X-DRAM Proof-of-Concept, Secures Strategic Investment to Advance AI Memory