PCIe 7.0 specification reaches "half way point"
By Nick Flaherty, eeNews Europe (April 3, 2024)
The latest version of PCI Express, PCIe 7.0, is on track for launch in 2025 with version 0.5 available today.
PCIe 7.0 updates the standard for PAM4 signalling to achieve 128 GT/s raw bit rate and up to 512 GB/s bi-directionally via x16 configuration while still being backwards compatible. Most leading systems are only now shipping PCIe 5.0 in chips, and PCIe 6.0 was released as a standard at the end of 2021.
The PCIe 7.0 technology is aimed to be a scalable interconnect solution for data-intensive markets including 800G Ethernet, artificial intelligence, machine learning, cloud hyperscaler data centres, high performance computing (HPC) and quantum computing.
To read the full article, click here
Related Semiconductor IP
- PCIe 7.0 Controller with AXI
- PCIe 7.0 Switch
- PCIe 7.0 Retimer Controller with CXL Support
- PCIe 7.0 Controller
- PHY for PCIe 7.0 and CXL
Related News
- Alphawave Semi at the Forefront of PCIe® 7.0 Specification: Showcasing Next-Gen Chiplet Interoperability and Optical PCIe Technology at PCI-SIG® Developers Conference 2025
- PCI-SIG Releases PCIe 6.0 Specification Delivering Record Performance to Power Big Data Applications
- Cadence Achieves PCIe 5.0 Specification Compliance for PHY and Controller IP in TSMC Advanced Technologies
- PCI-SIG® Announces PCI Express® 7.0 Specification to Reach 128 GT/s
Latest News
- IntoPIX & Altera Unlock New Levels Of Efficiency For JPEG XS On Agilex At IBC 2025
- Perceptia Begins Port of pPLL03 to Samsung 8nm Process Technology
- Efinix® Doubles Titanium Product Line
- SmartSoC Solutions Partners with Cortus to Advance Chip Design and Manufacturing for SIM Cards, Smart Cards, Banking Cards, and E-Passports in India
- Fraunhofer IIS and ARRI announce partnership for post-production workflows at IBC 2025