NurLogic announces the development of its 2.5GBPS PCI Express PHY IP Core

NurLogic’s PCI Express PHY IP Design Will Utilize NurLogic’s  Silicon-Proven 0.13-micron SerDes PHY Core

SAN DIEGO –February 19, 2003 – NurLogic Design, Inc. a developer of high bandwidth connectivity solutions today announced it is developing a multi-configuration 2.5Gbps OpalLinkTM PCI Express PHY IP Core in 0.13-micron technology.   NurLogic is currently developing a full line of serial link connectivity products for integration into high-end computing and communications applications.   

“As the pioneer and leader in mixed-signal IP, we provide our customers with proven integration expertise, lane, power and area scalability allowing our customers the flexibility to meet their design solutions now and into the future, ” said Behnam Malek-Khosravi, vice president of engineering for NurLogic.   “Our XAUI-compatible serial links are based on our silicon-proven SerDes Core and allow us to meet PCI Express specifications with room to spare.”  NurLogic’s modular design allows for multiple instantiations, enabling a broad range of computing and communications target applications emphasizing performance, cost and scalability.

Providing customers with PCI Express PHY IP solutions, based on its existing silicon-validated and characterized Quad 3.125Gbps SerDes PHY IP, fills an important need in the marketplace for reliable IP solutions.   “The industry is accelerating development of PCI Express products, underscoring the need for PCI Express components,” said Jim Pappas, director of Initiative Marketing for Intel’s Enterprise Platform Group.  “We’re pleased to see NurLogic make an announcement about their PCI Express plans at the Intel Developers Forum, Spring 2003.”

NurLogic is developing the industry’s smallest, low power, PCI Express PHY IP Core available on the market.  NurLogic’s OpalLink™ 8-Lane PCI Express IP core in 0.13-micron technology operates at 2.5Gbps/lane and will consume less than 80mW/lane of power.  NurLogic is currently developing additional next-generation serial link connectivity IP to add to its portfolio.

NurLogic Design is proud to announce its participation in the Intel Developers Forum, Spring 2003. NurLogic will be demonstrating PCI-Express compatible architecture in booth # 203 during IDF.

Availability
NurLogic's 0.13-micron PCI Express core will be available to license in Q2’03.  NurLogic will offer the OpalLink PCI Express PHY IP core as a “hard” IP block that will include support for leading EDA tools and foundry technologies.  A leader in analog and digital design, NurLogic provides expert integration support to help customers more easily integrate the OpalLink PCI Express core into their designs. Further information and pricing is available upon request.

About NurLogic Design, Inc.
NurLogic Design, Inc. provides high-bandwidth connectivity solutions to the networking and communications industries. NurLogic utilizes its expertise in analog/mixed-signal design and high-performance I/O bus interfaces to develop silicon-proven Intellectual Property (IP) to deliver value-add to its customers. NurLogic products are targeted at CMOS and silicon germanium technologies and include high-speed connectivity IP, analog and mixed-signal IP and foundation IP. Based in San Diego, California, NurLogic has regional sales offices in Massachusetts and Silicon Valley. NurLogic is a privately held corporation.

Headquarters: 5580 Morehouse Drive, San Diego, Calif. 92121. Tel: 1-877-NURLOGIC. On the web at www.nurlogic.com.

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