MorethanIP releases a new version of its 10/100/1000 Ethernet MAC Core featuring a configurable 8/32-Bit Client interface
May 25, 2003 - MorethanIP releases Version 3.2 of its 10/100/1000 Ethernet MAC Core featuring a configurable 8/32-Bit Client interface for improved system level and embedded processor performance. With Version 3.2 the integration with standard interfaces like PCI, POS-PHY L3 or SPI 4.2 becomes simpler and seamless with an Altera Atlantic compatible FIFO client interface.
For applications that require the implementation of embedded processor (e.g. Routing, Switching, Firewall, Masquerade,...) the 10/100/1000 MAC core is also available with a direct 32-Bit Avalon Bus Interface that provides seamless connectivity to Altera Niostm embedded processor environments. An integration with ARM processor with 32-bit AHB bus is planned.
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- LZ4/Snappy Data Compressor
Related News
- MIPS Technologies and TSMC form strategic alliance to deliver "hard" versions of MIPS 32 and 64 Bit Processor Cores
- MorethanIP ships 2nd Generation 10GbE MAC Core
- MorethanIP's 10/100/1000 Ethernet MAC Version 3 now with register map and full statistics support
- MorethanIP and Innocor announce the interoperability check of MorethanIP 10 Gigabit Ethernet MAC (Medium Access Control) and 10G-BaseR PCS (Physical Coding Sub-Layer) with Innocor’s 10 Gigabit Ethernet test solution
Latest News
- CAST Releases First Dual LZ4 and Snappy Lossless Data Compression IP Core
- Arteris Wins “AI Engineering Innovation Award” at the 2025 AI Breakthrough Awards
- SEMI Forecasts 69% Growth in Advanced Chipmaking Capacity Through 2028 Due to AI
- eMemory’s NeoFuse OTP Qualifies on TSMC’s N3P Process, Enabling Secure Memory for Advanced AI and HPC Chips
- AIREV and Tenstorrent Unite to Launch Advanced Agentic AI Stack