IP assembly represents a sea change in the design of ASICs

Time was when designing an ASIC meant generating RTL, from scratch, for every block in the design. As chip capacities grew larger, this approach became less efficient and, eventually, impractical. For several years now, the voice of orthodoxy has been saying that the only realistic way to design system-level ICs is through the extensive use of intellectual property.

IP use has gone through an evolution of its own. A couple of years ago, IP reuse meant, for most teams, repurposing blocks that had been designed for some other project. Often the boundaries of reuse coincided with the boundaries of the design team-differences in methodology and reuse practice meant that a team was unlikely to import blocks that had been done by someone else in the same company.

Today, we are seeing a much broader attempt at reuse. Some third-party IP items, such as ARM cores, have established themselves firmly in the system-on-chip repertoire. Hardly anyone designs his own 32-bit CPU anymore. There is a huge proliferation of other third-party IP, of varying accessibility and quality. And many companies have their own internal reuse standards that make virtually any block designed in the organization available to future designs.

This has led to the rise of a new term to describe ASIC design: IP assembly. The suggestion is that ASIC design now is different in kind from the days when we wrote new register transfer level for everything. Instead of designing, we are assembling prefabricated blocks into new configurations.

Somehow, the word doesn't match reality, though. A lot more goes into producing a working, yielding SoC than just putting things together. Not the least of the efforts is in creating new blocks to implement functions that aren't available as needed from the internal and external IP worlds. But the amount of work in "just" connecting the dots-floor planning, interconnecting the blocks correctly, placement and routing, timing, signal integrity and power closure and rule checking-can be huge. It can also require considerable creativity. And no one, other than an IP vendor, has suggested that employing existing IP reduces the verification task in the least.

Now it appears that we are seeing yet another stage in this evolutionary march. Under the banner of capital efficiency, companies are eliminating even the skeleton engineering teams necessary to do IP assembly, and hanging on only to hardware engineers with specific expertise on the blocks that can serve as end-product differential advantages. To have a hardware design at all, these teams are importing whole reference designs, including fully functional chip designs, verified firmware and even board layouts. They are applying their own expertise just to adding the features they believe will differentiate them in the end market. Sometimes that means practically no hardware changes at all.

In this scenario, very little change is being made to the chip design. The object is to disrupt as little as possible of each view of the design as it passes from behavioral simulation to tapeout.

Design has become an engineering change order process. Yet these teams are working with tools intended not for handling ECOs, but for doing full designs from a clean sheet of paper. It's a mismatch that someone will make a lot of money correcting.

Ron Wilson covers microprocessors, programmable/reconfigurable logic and the chip design process. He can be reached at rwilson@cmp.com.