Altera's Stratix IV FPGAs Pass Interlaken Interoperability Test
Devices Support Chip-to-Chip Interlaken Interface up to 10-Gbps Line Rates
San Jose, Calif., March 8, 2010 — Altera Corporation (NASDAQ: ALTR), today announced its Stratix® IV FPGAs passed the Interlaken Alliance's device interoperability testing. Altera certified its high-performance FPGAs interface with third-party components using the Interlaken protocol. Stratix IV GT FPGAs passed interoperability testing at 6.25-Gbps line rates and are the industry's only Interlaken solution capable of supporting line rates of 10 Gbps. Device interoperability testing validates Stratix IV FPGAs for chip-to-chip Interlaken interface and ensures they can be quickly deployed as a turnkey solution for next-generation wireless and wireline infrastructure applications.
Altera passed interoperability testing using a Stratix IV GT FPGA development board along with Altera's internally developed Interlaken intellectual property (IP) core. The IP core is fully compliant to the Interlaken Protocol Definition revision 1.2 and provides a cost-effective, risk-free solution that can be quickly implemented in the FPGA.
“The Interlaken protocol is a popular solution for equipment manufactures due to its ability to enable high-speed chip-to-chip packet transfers and Altera is committed to providing our customers a comprehensive Interlaken solution through our leading-edge FPGAs,” said Luanne Schirrmeister, senior director of component product marketing at Altera Corporation. “By offering an Interlaken solution that supports data rates up to 10-Gbps, Altera is driving the industry's move toward 100G systems.”
Passing the Interlaken Interoperability Test
The Interlaken Alliance's device interoperability test included five chip vendors testing the connectivity between their components using the Interlaken protocol. Altera successfully demonstrated interoperation with all the participating ASSP vendors' solutions, including Cortina's CS1999 and CS3477 device families and PMC-Sierra's HyPHY 20G platform.
“As demand for voice, video, and data increases, service providers are looking for ways to upgrade their existing infrastructure,” said Fred Olsson, product line director at Cortina Systems. “Proven interoperability between the Altera Interlaken IP core on Stratix IV hardware and Cortina's CS1999 40Gb/s framer as well as CS3477 aggregator ICs enables not only a seamless connection for high throughput packet processing but also further demonstrates Interlaken's ability to eliminate bandwidth restrictions and increase performance for communications applications that require the highest possible performance.”
Availability
Altera® Stratix IV FPGAs are available today in production. For pricing information contact your local Altera sales representative. Altera's internally developed Interlaken IP core is available by contacting Altera. For additional information regarding Altera's Interlaken solutions visit: www.altera.com/technology/high_speed/protocols/interlaken/pro-interlaken.html
About Altera
Altera programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate and win in their markets. Find out more about Altera's FPGA, CPLD and ASIC devices at www.altera.com.
Related Semiconductor IP
- Interlaken Controller
- Interlaken IP
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- Interlaken Core (Up to 600G)
- UltraScale / UltraScale+ Interlaken
Related News
- Chip Interfaces Successfully Completes Interlaken IP Interoperability Test with Cadence 112G Long-Reach PHY
- Synopsys Demonstrates Industry's First Interoperability of PCI Express 6.0 IP with Intel's PCIe 6.0 Test Chip
- Comcores and Extoll successfully completed the interoperability test of Comcores JESD204C IP core and Extoll SerDes PHY
- ARM Recipient of Synopsys Fifth Annual Tenzing Norgay Interoperability Achievement Award
Latest News
- How hardware-assisted verification (HAV) transforms EDA workflows
- BrainChip Provides Low-Power Neuromorphic Processing for Quantum Ventura’s Cyberthreat Intelligence Tool
- Ultra Accelerator Link Consortium (UALink) Welcomes Alibaba, Apple and Synopsys to Board of Directors
- CAST to Enter the Post-Quantum Cryptography Era with New KiviPQC-KEM IP Core
- InPsytech Announces Finalization of UCIe IP Design, Driving Breakthroughs in High-Speed Transmission Technology