How to take advantage of partial reconfiguration in FPGA designs

By Mark Goosman, Nij Dorairaj, and Eric Shiflet, Xilinx Corp.
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The obvious benefit of using reconfigurable devices, such as FPGAs, is that the functionality that a device has now can be changed and updated at some time in the future. As additional functionality is available or design improvements are made available, the FPGA can be completely reprogrammed with new logic. For many users, this still isn't enough. What if I want to change the logic within a part of an FPGA without disrupting the entire system? I may, for example, have a design comprised of several blocks of logic and, without disrupting the system and stopping the flow of data, need to update the functionality within one block. Thus, I need a way to partially reconfigure the application on a device.

Partial reconfiguration is a design process, which allows a limited, predefined portion of an FPGA to be reconfigured while the remainder of the device continues to operate. This is especially valuable where devices operate in a mission-critical environment that cannot be disrupted while some subsystems are being redefined.

Using partial reconfiguration, you can dramatically increase the functionality of a single FPGA, allowing for fewer, smaller devices than would otherwise be needed. Important applications for this technology include reconfigurable communication and cryptographic systems.

In an SRAM-based FPGA, all user-programmable features are controlled by memory cells that are volatile and must be configured on power-up. These memory cells are known as the configuration memory, and they define the look-up table (LUT) equations, signal routing, input/output block (IOB) voltage standards, and all other aspects of the design.

In order to program the configuration memory, instructions for the configuration control logic and data for the configuration memory are provided in the form of a bitstream, which is delivered to the device through the JTAG, SelectMAP, serial, or ICAP configuration interface.

An FPGA can be partially reconfigured using a partial bitstream. You can use such a partial bitstream to change the structure of one part of an FPGA design as the rest of the device continues to operate.

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