Xilinx And ISR Technologies Demonstrate World's First Software-Defined Radio Using Partial Reconfiguration of FPGAs

Technology dramatically reduces cost, power, and size of software-defined radios

The demonstration consists of a SD-IDU (Software Defined Indoor Unit) modem from ISR Technologies instantiating a wideband waveform in a Xilinx Virtex-II Pro FPGA to transmit video data to another SD-IDU. While maintaining transmission of the wideband waveform, the SD-IDU then initiates a narrowband waveform to also transmit voice data to the other SD-IDU. By supporting multiple waveforms in a single FPGA and seamlessly changing waveforms on a dynamic basis without disrupting current waveforms, this powerful technology can significantly lower the cost, power consumption and size of an SDR. Partial reconfiguration of FPGAs is enabling a new model of digital signal processing (DSP), known as a shared resources model, in SDR modems.

"Xilinx's DSP and Aerospace & Defense Divisions are very excited to be able to bring the promise of partial reconfiguration of FPGAs to fruition in this demonstration with ISR Technologies," said David Squires, director of DSP Division Marketing at Xilinx. "It is our expectation that this technology will transform the way DSP is done in key SDR programs, such as JTRS, resulting in lower cost tactical radios with longer battery life."

"The implementation of a shared resources model is of great significance to the SDR community," said Pierre-André Meunier, executive vice president of ISR Technologies. "We were pleased to be able to work with Xilinx to prove the technology could be supported in the SCA environment mandated for JTRS."

The Virtex-II Pro FPGA is the only signal processing device in the SD-IDU, so it also must manage the radio control functions, as well as the waveform processing. This is made possible by the embedded hard PowerPC 405 core of the Virtex-II Pro device. By running a real-time operating system, a CORBA ORB and Software Communications Architecture (SCA) Core Framework on an embedded 405 core, all the infrastructure necessary to manage the modem is available. This is the infrastructure mandated for JTRS by the US Department of Defense. This approach results in an SCA-enabled SDR System-On-a-Chip (SoC), which also reduces cost, power and size by eliminating the need for a discrete general-purpose processor.

Partial Reconfiguration of FPGAs
Partial reconfiguration is the ability for an application running on an FPGA to dynamically configure or reconfigure a portion of an FPGA to suit its needs, while other portions of the FPGA are under use by other applications. This is analogous to multi-threading of a general purpose processor (GPP). This technology enables support for multiple independent waveforms concurrently in a single device and supports independent loading and tearing down of waveforms.

Shared Resources Model
Partial reconfiguration of FPGAs is the requisite enabling technology to support a shared resources model, as opposed to a dedicated resources model. In a dedicated resources model, an SDR modem requires N sets of dedicated processing resources (i.e., N FPGAs, N DSPs, N GPPs) to support N waveforms. This inefficient implementation leads to a higher power, more expensive modem that does not scale well. In a shared resources model, less processing resources are required since multiple waveforms can be supported on a single set of processing resources. The result is a lower cost modem that consumes less power.

About ISR Technologies
ISR Technologies is a leading edge Software Defined Radio company. By combining ISR's extensive signal processing expertise with its state of the art Software Defined Radio (SDR) capabilities, ISR produces Software Defined Modems and Communications Subsystems that are unparalleled in flexibility, scalability, and performance. For more information, visit www.isr-technologies.com.

Xilinx is the worldwide leader in complete programmable logic solutions. For more information, visit www.xilinx.com.