Hidden IP: booby trap or buried treasure?
George Leopold, EE Times
(04/30/2007 9:00 AM EDT)
WASHINGTON — If the process by which technology standards are forged and implemented isn't broken, it is surely straining under the weight of globalization, relentless technological change, patent-infringement and antitrust lawsuits as well as increasingly noisy standards battles among competing industry consortia.
In response, standards bodies are reviewing their procedures for dealing with intellectual-property (IP) rights. Many are focusing on patent and licensing disclosure. The IEEE, for instance, is awaiting a government opinion on a plan to use voluntary patent disclosure in its standards proceedings (see story, below). Groups like VITA, the Digital Video Broadcasting Project and Jedec are either conducting similar reviews or contem- plating new disclosure requirements.
(04/30/2007 9:00 AM EDT)
WASHINGTON — If the process by which technology standards are forged and implemented isn't broken, it is surely straining under the weight of globalization, relentless technological change, patent-infringement and antitrust lawsuits as well as increasingly noisy standards battles among competing industry consortia.
In response, standards bodies are reviewing their procedures for dealing with intellectual-property (IP) rights. Many are focusing on patent and licensing disclosure. The IEEE, for instance, is awaiting a government opinion on a plan to use voluntary patent disclosure in its standards proceedings (see story, below). Groups like VITA, the Digital Video Broadcasting Project and Jedec are either conducting similar reviews or contem- plating new disclosure requirements.
To read the full article, click here
Related Semiconductor IP
- JESD204E Controller IP
- eUSB2V2.0 Controller + PHY IP
- I/O Library with LVDS in SkyWater 90nm
- 50G PON LDPC Encoder/Decoder
- UALink Controller
Related News
- Analogue Insight IP Group Launches Analogue Insight SAFE in Portland, Oregon to Deliver Certification-Grade Security IP for Next-Gen SoCs and Chiplets
- CAST Launches Multimedia Line with IP Cores for Image or Video Compression
- ARC International Next-Generation SoC Development Platform Targets “Six Months or Less” Design Cycle
- Xelic Announces Frame Mapped Generic Framing Procedure Core Availability for Integration into ASIC or FPGA Networking Applications
Latest News
- Barcelona Zettascale Lab advances European technological sovereignty as Cinco Ranch TC1 chip passes validation
- CoreHW Appoints Redtree as Pan-EMEA Sales Representative
- Imec inaugurates NanoIC pilot line, accelerating innovation in sub-2nm systems-on-chip
- Honda and Mythic Announce Joint Development of 100x Energy-Efficient Analog AI Chip for Next-Generation Vehicles
- PQSecure Collaborates with George Mason University on NIST Lightweight Cryptography Hardware Research