Hidden IP: booby trap or buried treasure?
George Leopold, EE Times
(04/30/2007 9:00 AM EDT)
WASHINGTON — If the process by which technology standards are forged and implemented isn't broken, it is surely straining under the weight of globalization, relentless technological change, patent-infringement and antitrust lawsuits as well as increasingly noisy standards battles among competing industry consortia.
In response, standards bodies are reviewing their procedures for dealing with intellectual-property (IP) rights. Many are focusing on patent and licensing disclosure. The IEEE, for instance, is awaiting a government opinion on a plan to use voluntary patent disclosure in its standards proceedings (see story, below). Groups like VITA, the Digital Video Broadcasting Project and Jedec are either conducting similar reviews or contem- plating new disclosure requirements.
(04/30/2007 9:00 AM EDT)
WASHINGTON — If the process by which technology standards are forged and implemented isn't broken, it is surely straining under the weight of globalization, relentless technological change, patent-infringement and antitrust lawsuits as well as increasingly noisy standards battles among competing industry consortia.
In response, standards bodies are reviewing their procedures for dealing with intellectual-property (IP) rights. Many are focusing on patent and licensing disclosure. The IEEE, for instance, is awaiting a government opinion on a plan to use voluntary patent disclosure in its standards proceedings (see story, below). Groups like VITA, the Digital Video Broadcasting Project and Jedec are either conducting similar reviews or contem- plating new disclosure requirements.
To read the full article, click here
Related Semiconductor IP
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
- MIPI CSI-2 CSE2 Security Module
- ASIL B Compliant MIPI CSI-2 CSE2 Security Module
Related News
- Analogue Insight IP Group Launches Analogue Insight SAFE in Portland, Oregon to Deliver Certification-Grade Security IP for Next-Gen SoCs and Chiplets
- CAST Launches Multimedia Line with IP Cores for Image or Video Compression
- ARC International Next-Generation SoC Development Platform Targets “Six Months or Less” Design Cycle
- Xelic Announces Frame Mapped Generic Framing Procedure Core Availability for Integration into ASIC or FPGA Networking Applications
Latest News
- Cadence Collaborates with TSMC to Accelerate Design of Next-Generation AI Silicon
- Synopsys Partners with TSMC to Power Next-Generation AI Systems with Silicon Proven IP and Certified EDA Flows
- JEDEC® Previews LPDDR6 Roadmap Expanding LPDDR into Data Centers and Processing-in-Memory
- Siemens collaborates with TSMC to advance AI for semiconductor design
- Crypto Quantique Unveils Latest Lightweight Cryptographic Primitives for Securing the Edge