CAST Launches Multimedia Line with IP Cores for Image or Video Compression

Flexible Discrete Wavelet and Cosine Transform cores from multimedia experts Alma Technologies ready for JPEG or MPEG applications

The new cores implement the popular discrete cosine transform (DCT) and emerging discrete wavelet transform (DWT) algorithms. Available now, they mark the beginning of a series of multimedia-related cores CAST expects to release over the next several months, culminating with a complete JPEG2000 core in mid-2002.

Multimedia Goes Mainstream

With the spread of Internet-based communication and wireless telephony, even mainstream designers need to employ compression algorithms and other functions previously used by multimedia specialists. The new cores make this expertise available in affordable, well-supported, reusable modules. With rigorously-defined interfaces and proven code, designers can integrate CAST multimedia cores with considerably less time and effort and greater reliability than they are likely to achieve implementing these functions themselves.

New Image/Video Compression Cores

The RC_2DDWT Discrete Wavelet Transform core implements the 2D Forward and Inverse Discrete Wavelet Transform (2D-DWT) using the lifting-based 5/3 and 9/7 filters. Hence, it is appropriate for wavelet-based image or video CODECS, and can be used as an IP core for products incorporating the JPEG2000 or MPEG4 standards. It is based on the row-column computational architecture. The company believes that is the only commercially-available core that implements both Forward and Inverse 2D-DWT.

Not an IP core itself, the 97FG is a VHDL code generator that produces optimized and synthesizable descriptions - cores - implementing the 9/7 Discrete Wavelet Transform's filter banks. The binary executable receives as inputs: i) the type of filter (forward or inverse), ii) the input bit-width, iii) a set of filter coefficients, and iv) the number of pipeline stages. It then generates the corresponding VHDL code for the specified 9/7 filtering unit, which can serve as an IP core for implementing DWT-based image and coding systems.

The DCT_FI core performs both the inverse and forward Discrete Cosine Transform (DCT) using either 8x8 or 16x16 pixel block samples. It is carefully designed to offer high performance while maintaining a low gate count - running, for example, at 70MHz on a Xilinx Virtex-6 FPGA - and it is ready for use in many multimedia, digital video and digital printing applications. Based on the row-column computational architecture, the DCT_FI core enables products performing compression/decompression with the JPEG, MPEG1, MPEG2, MPEG4, H.261, H.263 industry standards.

The new CAST multimedia cores are available today in VHDL for synthesis to ASICS or optimized for implementation with programmable devices from Altera and Xilinx. Custom core modifications, Verilog versions, or other options are also available.

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