Quintauris and Nuclei Collaborate to Expand RISC-V Solutions
The collaboration aims to enhance the compatibility and scalability of RISC-V solutions, accelerating the adoption of open standards across diverse industries.
Munich, Germany -- November 10, 2025 - Quintauris, a global provider of RISC-V-based products and Nuclei System Technology, a leading RISC-V processor IP vendor, today announced a new partnership. Through this collaboration, both companies will work together to enable the integration of Nuclei’s RISC-V processor IP into Quintauris reference platforms, contributing to a stronger, more cohesive RISC-V ecosystem.
Nuclei’s comprehensive RISC-V IP portfolio offers a versatile foundation for developing optimized and application-specific solutions, including automotive-grade options that are already production-ready. This partnership reinforces Quintauris’ commitment to bringing together key technology providers to secure the expected performance while it enables interoperable, reliable, and future-ready RISC-V implementations.
"Partnering with Nuclei allows us to strengthen the RISC-V ecosystem in China and secure global production solutions starting with automotive real-time cores," said Pedro Lopez, Market Strategy Officer, Quintauris.
"As a leading RISC-V processor IP vendor from China, we are excited to collaborate with Quintauris to promote a more connected and global RISC-V ecosystem, especially in the automotive sector. Nuclei offers a series of ISO 26262 certified RISC-V CPU IP products, featuring high flexibility and configurability to meet various requirements of automotive applications from ASIL-A to ASIL-D," said Dr. Jianying Peng, CEO, Nuclei. "Through this partnership, we aim to make our configurable and secure RISC-V cores more accessible for next-generation designs."
The integration of Nuclei’s IP within future Quintauris reference platforms will contribute to expanding the portfolio of verified and interoperable RISC-V building blocks, supporting the continued growth of the open computing movement.
Related Semiconductor IP
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- 32-Bit & 64-Bit High Performance Processor - 9-Stage Pipeline, Dual-issue
- 32-Bit & 64-Bit High Performance Processor - 6-Stage Pipeline, Single-issue
- RISC-V Debug & Trace IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
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