Why Opt For Chip Stack, FD-SOI in Image Sensors?
Junko Yoshida, EETimes
1/28/2016 02:30 PM EST
MADISON, Wis. -- If Samsung’s latest smartphone TV commercial (which touts a number of superior camera features and ends with a tagline -- “It's Not a Phone, It's a Galaxy”) is any indication, the ingredient that matters most in smartphones today isn’t the phone. It’s the camera.
As camera functions become essential to differentiate embedded devices, designers of CMOS image sensors (CIS) find themselves wrestling with growing demands on multiple fronts – image quality, size of camera modules and overall cost.
Over the last few years, CIS vendors have embraced chip stacking. Under that option, a CIS is stacked with an image signal processor (ISP). As the next step, at least two major players, Sony and Samsung, are reportedly pondering the use of FD-SOI wafers in manufacturing ISPs for a chip stacked CIS.
Related Semiconductor IP
- RISC-V CPU IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
Related News
- Sony To Use FD-SOI in Stacked Image Sensors
- CMOS Image Sensors See Higher Growth from Greater Diversity of Uses
- Sony Acquires Belgian Innovator of Range Image Sensor Technology, Softkinetic Systems S.A., in its Push Toward Next-Generation Range Image Sensors and Solutions
- CMOS Image Sensors Expected To Set Record-High Sales for Another Five Years
Latest News
- HPC customer engages Sondrel for high end chip design
- PCI-SIG’s Al Yanes on PCIe 7.0, HPC, and the Future of Interconnects
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- Cadence Unveils Arm-Based System Chiplet
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers