Design team says RISC processor is first diagonally interconnected IC

Design team says RISC processor is first diagonally interconnected IC
By Semiconductor Business News
February 6, 2002 (9:42 a.m. EST)
URL: http://www.eetimes.com/story/OEG20020206S0014

SAN FRANCISCO -- A 200-MHz RISC processor has become the first IC to be successfully laid out with diagonal interconnect lines as proposed under the "X Architecture" initiative, said a technical paper presented by Toshiba Corp., its ArTile subsidiary and Simplex Solutions Inc. at the International Solid-State Circuits Conference (ISSCC).

The paper said the X Architecture resulted in a 20% improvement in design performance and 10% savings in design area. The X Architecture now has 32 companies supporting the concept of diagonal interconnect lines instead of traditional wiring grids of right angles. The architecture and an initiative to promote it was launched eight months ago (see June 4 story).

"We believe that the benefits of this new architecture are so great that within a few years, most designs with five or more metal layers will be implemented using the X Architectu re," said Takashi Mitsuhashi, chief specialist of LSI system design at Toshiba and one of the paper's authors. "The initial results we outlined in our paper certainly support this belief."

The ISSCC paper, "A Diagonal Interconnect Architecture and its Application to RISC Core Design," described the use of X Architecture in a 200-MHz RISC processor design with 750,000 random logic gates, in addition to several SRAM and custom blocks. The 4.8 mm² chip design is targeted for 0.18-micron CMOS process technology, with 0.28-micron line spacings for signal routes.

The design was implemented with a "tile-based" design methodology developed by ArTile Microsystems Inc., which is a San Jose-based subsidiary of Toshiba America Electronic Components. The design team used Simplex Solutions Inc.'s "liquid routing" -- a physical design technology that enables pervasive diagonal routing. This aproach implemented random logic "tiles," and then integrated those tiles into IP blocks for conventional orthogona l interconnects.

The design team said the result was an overall 20% wire-length reduction and 10% area reduction. Static timing analysis confirmed a 20% performance improvement in all blocks.