Deal links formal verification to testbench generation

Deal links formal verification to testbench generation
By Michael Santarini, EE Times
September 5, 2001 (11:44 a.m. EST)
URL: http://www.eetimes.com/story/OEG20010905S0037

SAN MATEO, Calif. — Partnering with IBM Corp., Verisity Ltd. plans to license its e language to NoBug Consulting so that firm can create a translator between Verisity's SpecMan elite testbench generator and IBM's RuleBase and FoC formal verification tools.

The move is being termed another step toward creating the fabled intelligent testbench.

NoBug Consulting has joined Verisity's LicenseE program and will develop a specification compiler, said Francine Ferguson, Verisity vice president of worldwide marketing. The compiler will translate functional specifications written in IBM's Sugar formal spec language to Verisity's e verification language.

"NoBug will first concentrate on developing a Sugar to Verisity specification compiler so that people who have written formal specifications in Sugar will be able to use them in a simulation-based environment using SpecMan Elite," said Ferguson. "In the second phase, NoBug will develop or modify the compiler to allow people to take things written in e and translate them to Sugar to use IBM's formal model checker and the FoC semiformal technology."

'Unified solution'

Ferguson said in the development of the language compiler, Verisity and IBM's tools will provide "a unified solution where engineers will be able to leverage their specification language of choice in complex verification workbenches."

Verisity has similar partnerships with other EDA vendors of formal verification technology such as Cadence Design Systems Inc. Ferguson said such partnerships are a step toward creating an intelligent testbench — a "wouldn't-it-be-great-if" concept that Dataquest's chief EDA analyst, Gary Smith, has been driving.

The idea of an intelligent testbench is a tool that would automatically scan a given chip design and assign different partitions of the design to the verification tool best suited to each partition or blocks of the design. This, in theory, would speed the verificat ion process, which by many accounts consumes more than 70 percent of the overall chip design process.

"The intelligent testbench is an automation of the process that takes place today, but such a tool would not only automatically assign verification tasks but also tell engineers how much code coverage they are getting throughout the process," said Smith. "Today's tools and methodologies over-check some parts and undercheck other parts."

As a result, he said, only 64 percent of a given design is being checked today. "The intelligent testbench would ensure better coverage," Smith said.

Calling the Verisity/NoBug/IBM agreement a minor step, at best, toward the intelligent testbench, Smith said, "It's a translator and a way for Verisity to sell into IBM."