Asiczen Releases its CAN Verification IP
October 4, 2016 -- Asiczen Technologies announces the release of its UVM based CAN verification IP. azCAN is fully compliant with CAN specification 2.0. azCAN is a UVM based verification component (UVC) that can be used by IP and SOC makers to test their CAN interface design effectively and quickly.
This easy-to-use UVC can be easily integrated to any UVM based environment and can be used to generate a variety of scenario without much effort. CAN is a multi-master serial bus standard for connecting Electronic Control Units [ECUs] also known as nodes. Two or more nodes are required on the CAN network to communicate.
The complexity of the node can range from a simple I/O device up to an embedded computer with a CAN interface and sophisticated software. The node may also be a gateway allowing a standard computer to communicate over a USB or Ethernet port to the devices on a CAN network.

Related Semiconductor IP
- JPEG XL Encoder
- LPDDR6/5X/5 PHY V2 - Intel 18A-P
- ML-KEM Key Encapsulation & ML-DSA Digital Signature Engine
- MIPI SoundWire I3S Peripheral IP
- ML-DSA Digital Signature Engine
Related News
- CAST Reaches 200 CAN IP Core Customers
- Xilinx Announces First Reconfigurable End-To-End CAN Solutions For The Automotive Market
- Actel Adds LIN and CAN Cores to Extensive Library of IP for Automotive FPGAs
- Altium and Bosch extend CAN licensing to FPGAs
Latest News
- Are Synopsys Layoffs a Harbinger of the AI-Assisted Design Era?
- EnSilica to develop quantum-resilient secure processor chip for critical national infrastructure applications backed by £5m UK Government ‘Contract for Innovation’
- CAST Introduces JPEG XL Encoder IP Core for High- Quality, On-Camera Still-Image Compression
- PGC Strengthens Cloud and AI ASIC Acceleration with Synopsys’ Next-Generation Interface and Memory IP on Advanced Nodes
- IntelPro Licenses Ceva Wi-Fi 6 and Bluetooth 5 IPs to Launch AIoT Matter-Ready SoCs