ARM, Denali, Intel, Rambus, Samsung, and Synopsys Collaborate on DDR PHY Interface Specification for DDR-DRAM Memory System Design
-- The specification is being developed by expert contributors from recognized leaders in the semiconductor, IP and electronic design automation (EDA) industries, including: ARM, Denali, Intel, Rambus, Samsung, and Synopsys.
The DDR PHY Interface (DFI) specification defines an interface protocol between memory controller logic and PHY interfaces, with a goal of reducing integration costs while enabling performance and data throughput efficiency. The protocol defines the signals, timing, and functionality required for efficient communication across the interface. The specification is designed to be used by developers of both memory controllers and PHY designs, but does not place any restrictions on the how the memory controller interfaces to the system design, or how the PHY interfaces to the DRAM devices.
Specification available for download now at: http://www.ddr-phy.org/
Related Semiconductor IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- LLM AI IP Core
- Post-Quantum Digital Signature IP Core
- Compact Embedded RISC-V Processor
- Power-OK Monitor
Related News
- DDR PHY Interface Specification to be Unveiled Next Week at MemCon
- Denali DDR Controller IP Product Enables Mobileye's Next-Generation Automotive Technology
- Denali DDR IP Product Surpasses 200 Design Wins
- Next-Generation FlowThrough Security Processors Successfully Employs Denali DDR Controller IP
Latest News
- BrainChip and Parsons Sign Strategic Agreement to Accelerate Edge AI Defense Systems
- Ainekko Brings Open-Source Principles to AI Hardware with Launch of AI Foundry
- Arteris Selected by Axelera AI to Accelerate Computer Vision for Edge Devices
- Preliminary Characterisation Report for Perceptia’s pPLL08W in GF 22FDX Now Available
- VSORA Launches Europe’s Most Powerful AI Inference Chip