AMD strikes 'alliance' with Transmeta, licenses 64-bit and bus technologies
![]() |
AMD strikes 'alliance' with Transmeta, licenses 64-bit and bus technologies
By Semiconductor Business News
May 25, 2001 (7:55 a.m. EST)
URL: http://www.eetimes.com/story/OEG20010525S0017
SUNNYVALE, Calif.--In a move to increase competition with Intel Corp. in PC processors, Advanced Micro Devices Inc. today announced it has licensed the company's 64-bit x86-64 technology and HyperTransport chip-interconnect format to microprocessor startup Transmeta Corp. Transmeta, in nearby Santa Clara, plans to use AMD's technologies in future x86-compatible processors to extend its product line from 32-bit to 64-bit computing. AMD and Transmeta described their licensing agreement as an alliance to promote next-generation microprocessor standards. "AMD's x86-64 instruction extensions provide the best upward compatible path for adding 64-bit address capabilities to the x86 instruction set for the PC industry," said David R. Ditzel, vice-chairman and chief technology officer at Transmeta. The highly publicized startup, which launched its power-stingy Crusoe processor last year, is also moving to AMD's HyperTransport high-speed I/O bus tec hnology to offer faster links between chips inside computers, networking gear, and communications systems. Last February, AMD launched the HyperTransport bus promising to provide an I/O interconnect format that speeds communications between ICs by up to 48 times, compared to existing bus systems (see Feb. 14 story). AMD is lining up companies to form a HyperTransport bus consortium, which is expected to be launched later this year to derail Intel's 3GIO bus format for next-generation systems.
Related Semiconductor IP
- Temperature Glitch Detector
- Clock Attack Monitor
- SoC Security Platform / Hardware Root of Trust
- SPI to AHB-Lite Bridge
- Octal SPI Master/Slave Controller
Related News
- MIPS Technologies and TSMC form strategic alliance to deliver "hard" versions of MIPS 32 and 64 Bit Processor Cores
- Intelop announces 10 G bit Ethernet MAC + PCIe + AMBA 2.0 Core which Receives and Transmits 64 - 1518 Byte packets at full line rate and is customizable for implementing differentiated application features
- Sydaap develops World’s First 64 Bit Floating Point FFT/IFFT Hardware Accelerator for N = 4096
- MIPS I6500-F First High Performance 64 Bit Multi-Cluster CPU IP to Receive ISO 26262 and LEC 61508 Certification
Latest News
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- The world’s first open source security chip hits production with Google
- ZeroPoint Technologies Unveils Groundbreaking Compression Solution to Increase Foundational Model Addressable Memory by 50%
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- AheadComputing Raises $21.5M Seed Round and Introduces Breakthrough Microprocessor Architecture Designed for Next Era of General-Purpose Computing