Accellera Announces Standard for Tracking Soft Intellectual Property Usage through the Semiconductor Design and Development Process
Soft IP Tagging 1.0 now available at Accellera.org
NAPA, Calif. -- April 16, 2013 â Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards announces completion of its IP Tagging 1.0 standard. The standard provides a mechanism to track critical soft IP data throughout the entire chip design and development process such that it can be readily identified, tagged, and used again for future designs. Find out more and download the standard under open source license at www.accellera.org.
Using the Soft IP Tagging 1.0 standard, engineers now have the ability to easily determine if a block of IP is contained within a chip, if it is the correct version, and if it is a candidate for reuse. In addition, semiconductor foundries, providers of IP, and manufacturers of design tools now have a standard way to track IP usage and royalty information with their customers.
The chip design process can include editing, synthesis, timing, placement, wiring, and other steps. Normally, control of a third-party IP source is lost once the block of IP is licensed, unlocked, or otherwise made available in clear code. IP Tagging 1.0 facilitates a data-driven method to tag a block of IP and track âwhere usedâ for applications such as ownership, royalty calculations, and recognition. It also facilitates the implementation of version identification for applicable bug fixes and errata and allows tracking of other data.
"I would like to thank the members of the IP Tagging Working Group for their dedicated efforts in achieving this IP standard,â said Kathy Werner, Accellera's IP Tagging working group chair. âSoft IP Tagging 1.0 not only provides a mechanism for version control and bug tracking, but can be used to determine the compatibility of an IP block for reuse in a future design. Engineers can now feel confident there is a standard methodology built around IP reuse, tracking, and data control.â
The Soft IP Tagging 1.0 standard is available immediately for download under open source license at www.accellera.org.
About Accellera Systems Initiative
Accellera Systems Initiative is an independent, not-for profit organization dedicated to create, support, promote and advance system-level design, modeling and verification standards for use by the worldwide electronics industry. The organization accelerates standards development, and as part of its ongoing partnership with the IEEE, its standards are contributed to the IEEE Standards Association for formal standardization and ongoing change control. For more information, please visit www.accellera.org. For membership information, please email membership@accellera.org.
Related Semiconductor IP
- Lightweight and Configurable Root-of-Trust Soft IP
- Message filter
- SSL/TLS Offload Engine
- TCP/UDP Offload Engine
- JPEG-LS Encoder IP
Related News
- Breker Verification Systems Unveils Next-Generation Trek5 with Fully Compliant Support for Accellera Portable Stimulus Standard
- SystemC Ecosystem gets boost with Accellera's new SystemC CCI 1.0 Standard
- AMIQ EDA Announces its Design and Verification Tools Eclipse IDE Supports First Release of Accellera Portable Test and Stimulus Standard (PSS)
- UVM Reference Implementation Aligned with IEEE 1800.2-2020 Standard
Latest News
- RIVAI Launched China’s First Fully Self-Developed High- Performance RISC-V Server Chip
- Equal1 advances scalable quantum computing with CMOS-compatible silicon spin qubit technology
- TSMC Reports First Quarter EPS of NT$13.94
- Thalia joins GlobalFoundries’ GlobalSolutions Ecosystem to advance IP reuse and design migration
- Using UDE® to test virtual automotive RISC-V prototypes from Infineon