Accellera Board Approves Security Annotation for Electronic Design Integration Standard 1.0 for Release
New standard to identify security concerns for IP providers
Elk Grove, Calif. -- July 14, 2021 -- Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, announced today that its Board of Directors has approved the Security Annotation for Electronic Design Integration (SA-EDI) Standard 1.0 for release. Developed by the IP Security Assurance (IPSA) Working Group, the new standard is available for immediate download at no cost.
The SA-EDI Standard defines a specification that documents security concerns for hardware IP and its associated components when integrated into an IC. With the new standard, IP providers can either identify security concerns to mitigate within their IP or disclose the concerns to their integrator. The standard is design, product, and tool independent. Users of the SA-EDI standard can provide consistent security collateral in a uniform format.
“There has been tremendous interest from the stakeholders in the development of a standard to address security concerns for hardware IP,” stated Lu Dai, Chair of Accellera. “I’d like to congratulate the IPSA Working Group on their efforts in getting this standard into the hands of IP providers concerned with tackling and reducing security risk.”
“I am very proud of the work our team has done to get this standard out into the community,” stated Brent Sherman, IPSA Working Group Chair. “To develop SA-EDI, we focused on using existing standards that pertain to IP specification, design, verification, and integration where security risk is a significant concern, as well as known security concerns. Using this information, we were able to develop a standard that is low overhead, non-disruptive, and scalable across multiple target implementations. I look forward to the feedback from the community as we continue to evolve the standard.”
More information and Background on SA-EDI:
Accellera has resources available to learn more about the SA-EDI Standard 1.0 and how it can help IP providers identify security concerns. For more information, including a recording of a workshop at virtual DVCon U.S. 2021, visit the IP Security Assurance Working Group page.
Join Accellera to help influence the ongoing development of the standard. More information about membership can be found on the website.
About Accellera
Accellera Systems Initiative is an independent, not-for profit organization dedicated to create, support, promote and advance system-level design, modeling, and verification standards for use by the worldwide electronics industry. The organization accelerates standards development and, as part of its ongoing partnership with the IEEE, its standards are contributed to the IEEE Standards Association for formal standardization and ongoing change control. For more information, please visit www.accellera.org.
Related Semiconductor IP
- Rad-Hard GPIO, ODIO & LVDS in SkyWater 90nm
- 1.22V/1uA Reference voltage and current source
- 1.2V SLVS Transceiver in UMC 110nm
- Neuromorphic Processor IP
- Lossless & Lossy Frame Compression IP
Related News
- Accellera's Security Annotation for Electronic Design Integration Standard 1.0 Moves Toward IEEE Standardization
- InPsytech Tapes Out F2F SoIC Design Compliant with UCIE 2.0 Standard Enabling High-Speed Interconnects for 3D Heterogeneous Integration
- Accellera Board Approves Universal Verification Methodology for Mixed-Signal (UVM-MS) 1.0 Standard for Release
- Robust AI Demand Drives 6% QoQ Growth in Revenue for Top 10 Global IC Design Companies in 1Q25
Latest News
- SignatureIP Achieves PCI-SIG® PCIe® 5.0 Certification, Joining Elite Group on Official Integrators List
- GUC Monthly Sales Report – August 2025
- eSOL and Infineon Enter Strategic Partnership for Next-generation Automotive Platforms Based on RISC-V/TriCore/Arm Microcontrollers
- Synopsys and GlobalFoundries Establish Pilot Program to Bring Chip Design and Manufacturing to University Classrooms
- Cadence to Acquire Hexagon’s Design & Engineering Business, Accelerating Expansion in Physical AI and System Design and Analysis