AccelChip DSP Synthesis with IP-Explorer Technology to be demonstrated at SDR Forum
MILPITAS, CA – November 8, 2005
– AccelChip Inc., the industry’s leading provider of semiconductor Intellectual Property (IP) and software for MATLAB® and Simulink® DSP algorithms targeting FPGAs and ASICs, will be demonstrating its new IP-Explorer™ Technology at the 2005 Software Defined Radio Technical Conference and Product Exposition in Orange County, California November 14-18, 2005 in booth #113.
The company is also presenting a paper titled, “Exploration of Least-Squares Solutions of Linear Systems of Equations with Fixed-Point Arithmetic” on Monday November 14th, at 2:00 PM. Dr. Thomas Cesear of AccelChip looks at the finite-precision effects of the Cholesky, QR, and singular value decomposition (SVD) matrix inversion techniques when used in a Generalized Sidelobe Canceling (GSC) beamformer. The paper will also be available on the AccelChip website immediately following the conference. Please visit www.accelchip.com/papers.html for more information.
During the conference exposition the company will demonstrate the AccelChip® DSP Synthesis tool which reads in floating-point MATLAB, automates conversion to fixed-point, and synthesizes RTL (VHDL or Verilog) and Simulink models along with a self-checking testbench based on the original MATLAB. In addition, it will highlight the product’s new IP-Explorer Technology now included within AccelChip DSP Synthesis version 2005.4. This new technology extends the product’s ability to rapidly explore the design space for DSP algorithms by automating macro- and micro-architecture tradeoffs of key DSP building blocks. The result is an algorithmic synthesis solution with unparalleled automation and quality of results.
In addition to AccelChip DSP Synthesis with IP-Explorer technology, the company will be showcasing the newest linear algebra DSP IP core generators recently added to the popular AccelWare® Advanced Math Toolkit. These unique generators can be used in the deployment of adaptive filter algorithms commonly found in software defined radio solutions such as smart antenna beamforming applications.
About SDR Forum
The SDR Forum will be held at the Hyatt Regency in Orange County, California from Monday, November 14 through Friday, November 18. For more information about the conference or to register for the event, please visit www.sdrforum.org.
About the Company
AccelChip Inc. is the industry’s only provider of MATLAB-based algorithmic synthesis solutions, including DSP intellectual property (IP), for embedded DSP design. The company develops and markets design tools, integrated verification flows, and parametric IP toolkits that combine to automate the development and implementation of DSP algorithms in FPGAs and ASICs. AccelChip’s proven solution integrates the domain-specific DSP design environment (MATLAB) with industry-standard hardware design flows from Aldec, Altera, Cadence, Mentor Graphics, Synplicity, Synopsys, The MathWorks, and Xilinx. Founded in 2000, AccelChip is located in Milpitas, California, and has design centers in Portland, Oregon, and Carlsbad, California. AccelChip’s Web address is www.accelchip.com.
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- ECC7 Elliptic Curve Processor for Prime NIST Curves
- HBM4E PHY and controller
Related News
- UPMEM selects Semidynamics RISC-V AI IP for Large Language Model Application
- Avant Technology Appointed as Sales Representative in Asia for EnSilica's eSi-Crypto IP
- M31 Unveils Full Range of Automotive IP Solutions at ICCAD Illuminating the Future of Automotive Chip Development
- M31's 12nm GPIO IP Adopted by C*Core Technology, Powering Innovation in Advanced Process Automotive Chips
Latest News
- CAST Releases First Dual LZ4 and Snappy Lossless Data Compression IP Core
- Arteris Wins “AI Engineering Innovation Award” at the 2025 AI Breakthrough Awards
- SEMI Forecasts 69% Growth in Advanced Chipmaking Capacity Through 2028 Due to AI
- eMemory’s NeoFuse OTP Qualifies on TSMC’s N3P Process, Enabling Secure Memory for Advanced AI and HPC Chips
- AIREV and Tenstorrent Unite to Launch Advanced Agentic AI Stack