ASIC pioneer reinvents 3-D FPGAs
R. Colin Johnson, EE Times
(01/29/2010 3:35 PM EST)
PORTLAND, Ore.—Serial entrepreneur Zvi Or-Bach is touting a three-dimensional field-programmable gate array (FPGA) technology that he claims could achieve the densities of an application specific integrated circuit (ASIC). Or-Bach's new company, NuPGA, presented details about its 3-D FPGA technology Friday (Jan. 29) at the Applied Materials Technical Symposium on 3-D Interconnect in Santa Clara, Calif.
Or-Bach, a past winner of the EE Times Innovator of the Year Award, previously pioneered ASICs at eASIC and later at Chip Express. Last year, Or-Bach applied for a patent with Rice University on a graphite-based memory process for creating reprogrammable memory elements, which NuPGA is now using as anti-fuses for its 3D FPGAs.
To read the full article, click here
Related Semiconductor IP
- Simulation VIP for Ethernet UEC
- Bluetooth® Low Energy 6.2 PHY IP with Channel Sounding
- Simulation VIP for UALink
- General use, integer-N 4GHz Hybrid Phase Locked Loop on TSMC 28HPC
- JPEG XL Encoder
Related News
- GLOBALFOUNDRIES Fab 8 Adds Tools To Enable 3D Chip Stacking at 20nm and Beyond
- Chip execs see 20 nm variants, 3-D ICs ahead
- 3D Graphics on Xilinx ZC702 Board
- Xilinx Ships World's First Heterogeneous 3D FPGA
Latest News
- Spectral Design and Test Inc. and BAE Systems Announce Collaboration in RHBD Memory IP Development
- VSORA and GUC Partner on Jotunn8 Datacenter AI Inference Processor
- Mixel MIPI IP Integrated into Automotive Radar Processors Supporting Safety-critical Applications
- GlobalFoundries and Navitas Semiconductor Partner to Accelerate U.S. GaN Technology and Manufacturing for AI Datacenters and Critical Power Applications
- VLSI EXPERT selects Innatera Spiking Neural Processors to build industry-led neuromorphic talent pool