SM4 IP

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Compare 9 SM4 IP from 6 vendors (1 - 9)
  • SM4 Crypto Engine
    • The SM4 crypto engine includes a generic & scalable implementation of the SM4 algorithm which is the block cipher standard of China.
    • It is compliant with the GBT.32907-2016 specification and can support several cipher modes including authenticated encryption.
    Block Diagram -- SM4 Crypto Engine
  • SM4-XTS Multi-Booster
    • The SM4-XTS Multi-Booster crypto engine includes a generic & scalable implementation of the SM4 algorithm (a block cipher specified by the OSCCA) making the solution ideal for high-end applications (including key, tweak, input and output registers and Galois field multiplier).​​​​​
    Block Diagram -- SM4-XTS Multi-Booster
  • SM4-GCM Multi-Booster crypto engine
    • ASIC & FPGA
    • High throughput
    • Guaranteed performance with small packets
    Block Diagram -- SM4-GCM Multi-Booster crypto engine
  • Fast Inline Cipher Engine, AES-XTS/GCM, SM4-XTS/GCM, DPA
    • One input word per clock without any backpressure
    • Design can switch stream, algorithm, mode, key and/or direction every clock cycle
    • GCM: throughput is solely determined by the data width, data alignment and clock frequency
    • XTS: block processing rate may be limited by the number of configured tweak encryption & CTS cores; a configuration allowing 1 block/clock is available
    Block Diagram -- Fast Inline Cipher Engine, AES-XTS/GCM, SM4-XTS/GCM, DPA
  • SM4 Encoder and Decoder
    • Compliant with GBT.32907-2016
    • Support both encryption and decryption
    • Support ECB, CBC and multiple ciphering modes
    Block Diagram -- SM4 Encoder and Decoder
  • SM4 Cipher Engine
    • The SM4 IP core implements a custom hardware accelerator for the SM4 symmetric block cipher, specified in Chinese national standard GB/T 32907-2016, and ISO/IEC 18033-3:2010/Amd 1:2021.
    • Designed for easy integration, the core, internally expanding the 128-bit key, is capable of both encryption and decryption and features a simple handshake input and output data interface.
    Block Diagram -- SM4 Cipher Engine
  • Symmetric Cryptographic Intel® FPGA IP
    • The Symmetric Cryptographic Intel® FPGA IP is a hard IP core implementing AES and SM4 encryption and decryption
    • Typically, the AES and SM4 standards are used to protect the confidentiality of network data in 5G, data center, and IoT applications, but can be used to secure any high-speed data in transit
    • Additionally, the XTS profile can be used in data storage applications.
    Block Diagram -- Symmetric Cryptographic Intel® FPGA IP
  • Security Protocol Accelerator for SM3 and SM4 Ciphers
    • Highly customer configurable, silicon-proven security accelerator
    • Support for Chinese security SM3 and SM4 (modes: ECB, CTR, CBC, CCM, GCM, XTS) algorithms
    • Option: Differential Power Analysis (DPA) countermeasures for SM4
    • Built-in scatter/gather DMA capability offloads the host processor
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