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Symmetric Cryptographic Intel® FPGA IP

Overview

The Symmetric Cryptographic Intel® FPGA IP is a hard IP core implementing AES and SM4 encryption and decryption. Typically, the AES and SM4 standards are used to protect the confidentiality of network data in 5G, data center, and IoT applications, but can be used to secure any high-speed data in transit. Additionally, the XTS profile can be used in data storage applications.

 

Key Features

  • IP Functionality
    • Hard IP core with configurable soft IP wrapper
    • Supports AES-GCM Mode, with 128bit or 256bit key sizes and meets NIST 800-38D
    • Supports AES-XTS Mode, with 128bit or 256bit key sizes and meets NIST 800-38E
    • Supports SM4 Mode, with 128bit key size meeting OSCCA GB/T 32907-2016 
    • Hard IP additionally supports AES-CTR and AES-BulkECB Modes
    • Default support for MACsec, IPsec, generic GCM, generic XTS, and SM4 profiles
    • Optimized for MACsec and IPsec, and can be used for DTLS, TLS1.3, QUIC, secure computing, and storage device encryption
    • Supports interleaved profiles
  • Performance specifications
    • NIST CAVP certified and OSCCA compliant
    • 200Gbps cumulative throughput capability per instance. of encryption and decryption.
    • Two or Four Hard IP instances per device (OPN dependent) giving up to 800Gbps total throughput
  • User and system interfaces
    • AXI4 Streaming interfaces for the data
    • AXI-Lite interface for management path
  • Debug and test capabilities
    • Error detection and logging capability
    • Testbench and example design available

Block Diagram

Symmetric Cryptographic Intel® FPGA IP Block Diagram

Technical Specifications

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