Emmc IP

Compare 60 IP from 16 vendors (1 - 10)

eMMC 5.1 Host Controller
- Compliant with eMMC Specification Version 5.0
- Supports one of the following System/Host Interfaces: AHB, AXI or OCP
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28HPM-NS
- Silicon proven, fully compliant core
- Premier direct support from IP core designers
- Easy-to-use industry standard test environment
SD 3.0 / SDIO 3.0 / eMMC 5.0 Host Controller
- Memory Card / Form Factors:
- IP Details:
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28HPM-EW
- • Suitable for Transmitter, Receiver, and Data Strobe pins
- VCORE Pre driver voltage
- VCCQ Post driver voltage
- TJ Junction temperature
eMMC Device Controller
- Compliant to the eMMC Electrical Standard 5.1A
- Supports Backwards Compatible, High Speed SDR, High Speed DDR, HS200 and HS400 transfer modes
- Host transfer rate of up to 400 MByte/s in HS400 mode
SD 5.1 / eMMC 5.1 Host Controller IP
- SD IP Features :
- Support SD system specification version 5.1
- Support Application Performance Class 1.
- Backward compatible to SD2.0 host
SD 4.1 / SDIO 4.0 / eMMC 5.1 Host Controller
- Fully compliant core with proven silicon
- Premier direct support from Arasan IP core designers
- Easy-to-use industry standard test environment
eMMC 5.1 Device Controller
- Compliant with eMMC 5.1 specification
- Peak bandwidth of 3.2 Gbps or 400 MB/s
- Additional Data Strobe signal for HS400 mode
IO 3.3V eMMC in GF (22nm)
- Completely hardened PHY solution along with programmable delay chains & I/Os
- Fully selectable output impedance
- Compliant with eMMC 5.1 (JESD84-B51A) and SDIO 3.0 JEDEC Standard
- Automotive G1/G2 supported, ASIL-B certified
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 16FFC NS
- • Suitable for Transmitter, Receiver, and Data Strobe pins
- VCORE Pre driver voltage
- VCCQ Post driver voltage
- TJ Junction temperature

eMMC IP