IP Catalog > EMMC

eMMC IP

Filter
Filter

Login required.

Sign in

Login required.

Sign in

Login required.

Sign in

Search (86)
Compare 86 IP from 20 vendors (1 - 10)
  • Simulation VIP for eMMC
    • High speed modes
    • 200 MB/s Read and Write operation. HS400 Dual Data Rate Read and Write interface
    • General eMMC Functionality
    • 48-bit input command format and R1, R1b, R2 response formats
    Block Diagram -- Simulation VIP for eMMC
  • eMMC Verification IP
    • Supports eMMC standard JESD84-A441, JESD84-B45, JESD84-B50, JESD84-B51 and JESD84-B51A specification.
    • Supports stream transfer operations.
    • Supports three different data width bus modes
    • 1-bit(default)
    Block Diagram -- eMMC Verification IP
  • eMMC Synthesizable Transactor
    • Supports eMMC standard JESD84-A441, JESD84-B45, JESD84-B50, JESD84-B51 and JESD84-B51A specification.
    • Supports stream transfer operations.
    • Supports three different data width bus modes
    • 1-bit(default)
    Block Diagram -- eMMC Synthesizable Transactor
  • eMMC Host Controller IIP
    • Compliant with JESD84-B50 Specification and earlier versions
    • Compliant with JEDEC eMMC CQHCI for Command Queuing
    • SD host controller Specification 6.0 compliant
    • Supports different data bus width modes : 1-bit, 4-bit, 8-bit.
    Block Diagram -- eMMC Host Controller IIP
  • eMMC Device Controller IIP
    • Compliant with JESD84-B51 Specification and earlier versions
    • Compliant with JEDEC eMMC CQHCI for Command Queuing
    • Supports different data bus width modes : 1-bit, 4-bit, 8-bit.
    • Supports Command queuing
    Block Diagram -- eMMC Device Controller IIP
  • eMMC v5.1/A Verification IP
    • Compliant with JEDEC eMMC version JESD84 - B51 and JESD84 – B51A.
    • Supports eMMC devices from all leading vendors.
    • Supports configuration for both host and device.
    • Support all data widths 1x, 4x, and 8x.
    Block Diagram -- eMMC v5.1/A Verification IP
  • eMMC LDPC Encoder/Decoder
    • Supports data rates from 50 MB/s to 9.0 GB/s.
    • Enables custom LDPC core development for specific requirements.
    • Wide range of codeword sizes.
    • Maximum supported parity.
    Block Diagram -- eMMC LDPC Encoder/Decoder
  • eMMC Device Controller
    • Compliant to the eMMC Electrical Standard 5.1A
    • Supports Backwards Compatible, High Speed SDR, High Speed DDR, HS200 and HS400 transfer modes
    • Host transfer rate of up to 400 MByte/s in HS400 mode
    Block Diagram -- eMMC Device Controller
  • eMMC/SDIO/SD
    • Compliant with eMMC5.1 specifications, up to 200MHz
    • Support HS400, HS200, High-Speed DDR, High-Speed SDR, and back compatible with legacy eMMC interface
    • Support Enhanced Strobe in HS400
    • Compliant with SD3.01/SDIO3.00 specifications, up to 208MHz
  • IO 3.3V eMMC in GF (22nm)
    • Completely hardened PHY solution along with programmable delay chains & I/Os
    • Fully selectable output impedance
    • Compliant with eMMC 5.1 (JESD84-B51A) and SDIO 3.0 JEDEC Standard
    • Automotive G1/G2 supported, ASIL-B certified
×
Semiconductor IP