eMMC 4.51 is the latest specification released by JEDEC and is designed to meet the requirements for secure yet flexible program code and data storage for consumer electronic products. With its low-pin count, high bandwidth and multiple boot mechanisms eMMC 4.51 greatly simplify system design for new products.
The eMMC 4.51 Device Controller IP is compliant with the latest eMMC specification. The controller provides a bandwidth of up to 1.6Gb/s in 200 MHz modes. A NAND Flash memory device can be connected to the eMMC memory controller. In such an implementation, the controller’s AHB interface provides a channel for data transfers between the memory controller and a NAND flash controller (also available from Arasan).
The eMMC 4.51 Device Controller supports the newer eMMC functions such as E2MMC devices, extended partitioning, command packing, context IDs, data tags and dynamic device capacity. The memory controller operates at a maximum frequency of 200 MHz. The eMMC interface supports MMC 1-bit, 4-bit, and 8-bit modes. eMMC supports power-on booting without the upper level of software driver which simplifies system design. The controller shields the host system from the functional differences among various NAND flash architectures (such as MLC). The explicit sleep mode allows the host to instruct the controller to directly enter a low power sleep mode. The controller supports block lengths or sector sizes of 512, 1024, 2048 and 4096 bytes.
