IP Catalog > UCIe Controller

UCIe Controller IP

Filter
Filter

Login required.

Sign in

Login required.

Sign in

Login required.

Sign in

Search (47)
Compare 47 IP from 9 vendors (1 - 10)
  • UCIe Controller add-on CXL2 Protocol Layer

     

    • UCIe Controller add-on CXL2 Protocol Layer
    Block Diagram -- UCIe Controller add-on CXL2 Protocol Layer
  • UCIe Controller add-on CXL3 Protocol Layer
    • UCIe Controller add-on CXL3 Protocol Layer
    Block Diagram -- UCIe Controller add-on CXL3 Protocol Layer
  • UCIe Controller baseline for Streaming Protocols for ASIL B Compliant, AEC-Q100 Grade 2
    • UCIe Controller baseline for Streaming Protocols for ASIL B Compliant, AEC-Q100 Grade 2
    • Low latency controller for UCIe-based multi-die designs
    • Includes Die-to-Die Adapter layer and Protocol layer
    Block Diagram -- UCIe Controller baseline for Streaming Protocols for ASIL B Compliant, AEC-Q100 Grade 2
  • The UCIe CONTROLLER IP
    • The UCIe IP solution includes D2D Adapter layer which supports streaming/PCIe/CXL/Raw flitformats, supports both standard and advanced mainband links and sideband links
    Block Diagram -- The UCIe CONTROLLER IP
  • UCIe Controller baseline for Streaming Protocols
    • Low latency controller for UCIe-based multi-die designs
    • Includes Die-to-Die Adapter layer and Protocol layer
    • Supports on-chip interconnect fabrics including AXI, CHI C2C, CXS, PCIe, CXL, and streaming
    • Error detection and correction with optional CRC and retry functionality
    Block Diagram -- UCIe Controller baseline for Streaming Protocols
  • UCIe Die-to-Die Controller IP
    • GammaCORE is a highly configurable and customizable Universal Chiplet Interconnect Express (UCle™) Die-to-Die Controller IP implementing the latest UCIe 2.0 specification and supporting UCIe Streaming protocol applications.
    • With the AresCORE D2D PHY IP, GammaCORE provides the complete UCIe solution for an open and robust chiplet ecosystem.​
    Block Diagram -- UCIe Die-to-Die Controller IP
  • UCIe PHY & Controller
    • Lightweight die-to-die interconnect solution consisting of the Physical Layer, Die-to-Die Layer and Protocol Layer optimized for highest performance with the lowest power and area overhead that is compliant to the Universal Chiplet Interconnect Express (UCIe) 2.0 specification.
  • UCIe Chiplet PHY & Controller
    • Compliant with the UCIe specification (2.0 & 1.1)
    • Flexible Structure, easy to customize (Pre-hardened PHY tuned to Customer Spec, PHY + Adapter Layer, PHY + Adapter Layer + Customized Protocol Layer)
    • Supports the CXS/AXI using the streaming package (AXI Interface bandwidth up to 89%)
    Block Diagram -- UCIe Chiplet PHY & Controller
  • UCIe Die-to-Die Chiplet Controller
    • High configurability and customizability
    • Defines packets to communicate with a link partner using different AXI parameters
    • Supports raw streaming modes
    • Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
    Block Diagram -- UCIe Die-to-Die Chiplet Controller
  • IPTD2D-A PHY and Controller
    • Our mass production-proven IPTD2D-A D2D Interconnect IP Solutions offer industry-leading power efficiency, performance, and low latency, tailored for the next generation of high-performance computing, AI, and data center applications.
    • With asynchronous “side-band” signals, the IPTD2D PHY can work at any frequency ranging from 2Gbps to 16Gbps, achieving the best balance between total bandwidth and power consumption.
×
Semiconductor IP