UCIe Controller IP

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Compare 44 IP from 6 vendors (1 - 10)
  • UCIe Controller baseline for Streaming Protocols
    • Low latency controller for UCIe-based multi-die designs
    • Includes Die-to-Die Adapter layer and Protocol layer
    • Supports on-chip interconnect fabrics including AXI, CHI C2C, CXS, PCIe, CXL, and streaming
    • Error detection and correction with optional CRC and retry functionality
    Block Diagram -- UCIe Controller baseline for Streaming Protocols
  • Universal Chiplet Interconnect Express (UCIe 1.0) Controller
    • Package Flexibility
    • Power Efficiency
    • Low Latency
    Block Diagram -- Universal Chiplet Interconnect Express (UCIe 1.0) Controller
  • UCIe Die-to-Die Chiplet Controller
    • High configurability and customizability
    • Defines packets to communicate with a link partner using different AXI parameters
    • Supports raw streaming modes
    • Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
    Block Diagram -- UCIe Die-to-Die Chiplet Controller
  • UCIe Die-to-Die Controller IP
    • High Configurability and Customizability
    • Comprehensive Verification
    Block Diagram -- UCIe Die-to-Die Controller IP
  • TSMC N3P Source Sync 3DIO PHY
    • Optimized for heterogeneous integration in 3D stacking
    • Enabling designers the flexibility and scalability to accelerate multi-die integration
    • Optimal PPA architected to supporting 2.5D and 3D packages
    • Versatile offering tuned for optimal use scenarios, including:
  • TSMC N3P Source Sync 3DIO Library
    • Optimized for heterogeneous integration in 3D stacking
    • Enabling designers the flexibility and scalability to accelerate multi-die integration
    • Optimal PPA architected to supporting 2.5D and 3D packages
    • Versatile offering tuned for optimal use scenarios, including:
  • TSMC N3P 3DIO Library
    • Optimized for heterogeneous integration in 3D stacking
    • Enabling designers the flexibility and scalability to accelerate multi-die integration
    • Optimal PPA architected to supporting 2.5D and 3D packages
    • Versatile offering tuned for optimal use scenarios, including:
  • TSMC N5 Source Sync 3DIO Library
    • Optimized for heterogeneous integration in 3D stacking
    • Enabling designers the flexibility and scalability to accelerate multi-die integration
    • Optimal PPA architected to supporting 2.5D and 3D packages
    • Versatile offering tuned for optimal use scenarios, including:
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Semiconductor IP