UCIe PHY & Controller

Overview

Lightweight die-to-die interconnect solution consisting of the Physical Layer, Die-to-Die Layer and Protocol Layer optimized for highest performance with the lowest power and area overhead that is compliant to the Universal Chiplet Interconnect Express (UCIe) 2.0 specification.

Key Features

  • Supports transfer rates of up to 32 Gbps/pin for up to 8Tbps with 10.5Tbps/mm of die edge bandwidth
  • Supports PCIe, CXL and streaming protocols adaptable to any communication protocols including extending the vendor's Non-Coherent and Coherent NOC interconnects across multiple dies
  • Built-in link initialization
  • Supports major 2.5D inter-die packaging technologies and standard packaging technologies
  • Supports internal and external (PHY-to-PHY) loopback test
  • Supports built-in self-test and repair functionality to maximize post-package yield

Technical Specifications

Short description
UCIe PHY & Controller
Vendor
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Semiconductor IP