TSMC 16nmFF+ 28G SerDes IP
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3.3V Capable GPIO on TSMC 28nm RF HPC+
- The 3.3V capable GPIO is an IP macro for on-chip integration. It is a 3.3V general purpose I/O built with a stack of 1.8V thick oxide MOS devices. It is controlled by 0.9V (core) signals.
- Supported features include core isolation, output enable and pull enable. Extra features such as input enable/disable, programmable drive strength and pull select, can be supported upon request.
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1.2V Thin Oxide GPIO on TSMC 28nm RF HPC+
- The 1.2V Thin Gate GPIO is an IP macro for on-chip integration. It is a 1.2V general purpose I/O that does not rely on thick-gate devices. Only thin-gate, 0.9V capable core MOS devices are used in the design.
- Supported features include core isolation, programmable slew rate compensation, programmable drive strength, input/output enable, pull select and pull enable. Extra features such as programmable hysteresis can be supported upon request.
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13-bit, 80 MSPS ADC - TSMC 65nm
- The A13B80M is a low-power, high-speed analog to digital converter (ADC) intellectual property (IP) design block.
- It is a hybrid-SAR ADC, with 13-bit resolution and a sampling speed of 80 megasamples per second (MSPS).
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12-bit, 200 MSPS Pipeline ADC - TSMC 28nm
- The A12B200M is a low-power, analog to digital converter (ADC) intellectually property (IP) design block.
- It is a hybrid successive approximation register (SAR) ADC, with 12-bit resolution, and a sampling speed of 200 megasamples per second (MSPS).
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TSMC CLN5FF GUCIe LP Die-to-Die PHY
- IGAD2DY11A is an LP (Low Power) Die-to-Die (D2D) PHY for SoIC-X Face-to-Face advanced package.
- This GUCIe PHY not only supports UCIe specification rev 1.1 compliance physical layer and Raw D2D interface (RDI) but also optionally provides the
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Flipchip 1.8V/3.3V I/O Library with ESD-hardened GPIOs in TSMC 12nm FFC/FFC+
- A 1.8V/3.3V flip-chip I/O library with ESD-immune GPIOs and integrated POC circuitry in TSMC FFC/FFC+.
- This library is a production-ready I/O library built on the TSMC 12nm process. The library features 1.8V to 3.3V GPIOs with programmable drive strength, hysteresis, and control logic.
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TSMC CLN3FFP HBM4 PHY
- IGAHBMZ03A is a High Bandwidth Memory 4 Physical Layer (HBM4 PHY) that is compliant with JEDEC HBM4 DRAM Specification JESD270-4.
- Fabricated in the TSMC 3 nm Advanced process node (N3P), it supports the data rate up to 12 Gbps per data pin in the DDR PHY Interface (DFI)-like 1:4 clock frequency ratio (HBM4 controller clock: WDQS = 1:4).
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Ku-Band Phased Array Tx-FE in TSMC 180nm RF
- The TRV801TSM180RF IP is a Ku-Band (14GHz to 14.5GHz) Transmitter (Tx) in TSMC 180nm RF CMOS process technology.
- It integrates X+Y transmitter channels on the same die and its low power makes it especially suitable for use in high-throughput modular digital Phased-Array Antenna products for mobile/tethered satellite communication applications.
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Ku-Band Phased Array Rx-FE in TSMC 180nm RF
- The TRV501TSM180RF IP is a Ku-Band (10.7GHz to 12.75GHz) Receiver (Rx) RFFE TSMC 180nm RF CMOS process technology.
- It integrates X+Y receiver channels on the same die and its low noise figure and wide baseband bandwidth makes it especially suitable for use in high-throughput modular digital Phased-Array Antenna products for mobile/tethered satellite communication applications.
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1.8V/3.3V I/O library with ODIO and 5V HPD in TSMC 16nm
- A 1.8V/3.3V flip-chip I/O library with 4kV HBM ESD protection, I2C compliant ODIO and Hot-Plug Detect.
- This library is a production-quality, silicon-proven I/O library in TSMC 16nm technology.
- Supports multi-voltage GPIOs, capable of operating at 1.8V or 3.3V, dynamically selectable at the system level.
