Multi Rail LDO for SERDES on TSMC CLN2P

Overview

The regulator macro addresses typical SOC power supply and other voltage regulation needs in a fully integrated easy-to-use macro. The output voltage may be programmed to be proportional to the input supply VIN or local bandgap reference voltage. This LDO has three independently programmable outputs.

Specifications Description Symbol Min Typ Max Units Regulator Power Voltage Input VIN 1.08 1.2 1.32 V Regulator Power Voltage Outputs VOUT 0.65 0.75 0.9 V VOUT Precision (untrimmed) -5 - 5 % Operational Temperature TOP -40 25 125 °C EM Temperature TEM - - 105 °C Load Current-VOUTT IVOUTT 150 mA Load Current-VOUTL IVOUTL 300 mA Load Current-VOUT IVOUT 300 mA Load Current Total 750 mA Area 0.0525 sq.mm Startup Time - - 10 us Output Voltage Step Resolution - 20 - mV Table 1: Specifications LDO Pin Description Pin Type Function VIN Power Input Power (1.2V) VOUTT VOUTL Power Output Power to Loads (0.75V) VOUT ENA Input Regulator Enable IREF Input Regulator current reference input from bandgap VOUTT_SEL[3:0] Output voltage select. Default setting= 0000 VOUTL_SEL[3:0] Input Trim can be applied as an offset to the VOUT_SEL code VOUT_SEL[3:0] CONFIG[3:0] Input Reserved ANA_TEST_SEL[1:0] Input Select for Analog Test Bus ANA_TEST_OUT Output Output for Analog Test from 0 to VOUT. Do not add digital buffers.

Table 2: Primary LDO Pin Description

Key Features

  • Easy to integrate with no special power requirements
  • Easy to use and configure
  • Programmable output level
  • Trimming supported using 4-bit control
  • Implemented with Analog Bits’ proprietary architecture

Technical Specifications

Foundry, Node
TSMC CLN2P
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Semiconductor IP