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Silicon Creations IP

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Compare 27 IP from 1 vendors (1 - 10)
  • 250Mbps to 12.7Gbps Multiprotocol SerDes PMA
    • Very wide CDR range -- operates with data rates from 0.25Gbps to 12.7Gbps
    • Extremely low jitter suitable for Enterprise SerDes applications
    Block Diagram -- 250Mbps to 12.7Gbps Multiprotocol SerDes PMA
  • Low Power Multiprotocol SerDes PMA
    • Very wide CDR range - operates with data rates from 0.6Gbps to 4.0Gbps
    • Compatible with JESD204A, JESD204B, OIF-CEI-6G-SR, CPRI, SGMII, XAUI and V-by-One
    Block Diagram -- Low Power Multiprotocol SerDes PMA
  • SGMII SerDes
    • Separate PLLs for Tx and Rx
    • Compatible with arbitrary numbers of parallel lanes
    • 10bit datapath for TX and RX
    • Flexible driver and receiver circuits compatible with LVDS, 4b current programming
    Block Diagram -- SGMII SerDes
  • Low Power Multiprotocol SerDes PMA
    • Very wide CDR range { operates with data rates from 0.6Gbps to 6.25Gbps
    • Compatible with JESD204A, JESD204B, OIF-CEI-6G-SR, CPRI, SGMII, XAUI and V-by-One
    Block Diagram -- Low Power Multiprotocol SerDes PMA
  • Jitter Cleaner PLL Digital Loop Filter
    • Automatically locks over an extremely wide input frequency range
    • Dual-loop PLL effective loop bandwidth can be arbitrarily small
    Block Diagram -- Jitter Cleaner PLL Digital Loop Filter
  • 32kHz Ultra-Fast-Lock IoT PLL
    • Input frequency range includes 32.768kHz
    • Output frequency range: <10MHz to >200MHz
    • Ultra-fast start-up. Frequency calibration ensures Fout is within 2% in <1.4ms from cold start
  • Precision Power-on Reset Generator
    • Monitors either 2 power domains ( 0.9V & 1.8V ) or 3 power domains ( 0.9V & 1.8V & 3.3V) per selection via digital control input.
  • XAUI Transciever
    • Chip-chip/backplane SerDes with 4 lanes each with data rates of 1.0Gbps to 3.125Gbps
    • Compatible with XAUI and custom back-planes
    • Deemphasis control for line driver compensates for PCB/backplane losses
    • Shared bias and TXPLL common blocks saves die area and power
  • JESD204B Serializer
    • Data rates of 1.6Gbps to 7.4Gbps per lane for up 29.6Gbps aggregate
    • Supports a single reference clock from 40MHz to 740MHz
    • JESD204B compatible with OIF-CEI 2.0 LV-OIF-6G-SR AC compliance
    • Shared common block includes TxPLL and bandgap reference
  • Ultra-Low Phase Noise Digital LC PLL
    • Wideband integrated jitter <400fs in integer mode, <800fs in fractional mode with high-speed / clean reference with active fractional noise cancellation
    Block Diagram -- Ultra-Low Phase Noise Digital LC PLL
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